Kalle Raiskila
2320a44b90
Make SPU backend not assert on jump tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 11:00:02 +00:00
Evan Cheng
fb3611daad
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 07:26:32 +00:00
Bill Wendling
3cbae239bb
Don't create a StringRef with a NULL value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 01:33:39 +00:00
Evan Cheng
0ce537a9db
Model some vst3 and vst4 with reg_sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 01:19:40 +00:00
Bill Wendling
81043ee5dc
The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
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string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.
Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 00:30:02 +00:00
Evan Cheng
e9e2ba05de
Model some vld3 instructions with REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a
Model vld2 / vst2 with reg_sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 17:34:18 +00:00
Kalle Raiskila
26c4cf4c6f
Fix encoding of 'sf' and 'sfh' instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 08:13:49 +00:00
Nathan Jeffords
bb59732d18
updated handling dllexport in X86AsmPrinter
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changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-09 08:40:06 +00:00
Nathan Jeffords
071de920a0
made COFF target dllexport logic apply to all subtargets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-09 05:52:28 +00:00
Chris Lattner
b54b9ddaaf
break coff symbol definition stuff out into proper MCStreamer callbacks,
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patch by Nathan Jeffords!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-08 19:54:22 +00:00
Jim Grosbach
4b77f6a85a
Clean up the conditional for handling of sign_extend_inreg based on
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whether the extract instructions are available.
rdar://7956878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:34:55 +00:00
Devang Patel
ed66bf5125
Use overloaded operators instead of DIDescriptor::getNode()
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:19:32 +00:00
Kalle Raiskila
021b5ef903
Testing svn access with a note added to documentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 18:06:28 +00:00
Chris Lattner
eb40a0fd98
switch MCSectionCOFF from a syntactic to semantic representation,
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patch by Peter Housel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103267 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 17:17:41 +00:00
Evan Cheng
435d499177
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 01:54:08 +00:00
Dan Gohman
0d881042c0
When rematerializing, use the debug location of the original
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instruction, rather than a location near where the new instruction
is being inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 01:28:10 +00:00
Evan Cheng
c10b5afbe8
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-07 00:24:52 +00:00
Daniel Dunbar
c26ae5ab7e
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
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- This fixes "leal 0, %eax", for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 22:39:14 +00:00
Chris Lattner
e1611f26e3
fix rdar://7947167 - llvm-mc doesn't match movsq
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 21:48:14 +00:00
Sean Callanan
1a8b789a4b
Eliminated the classification of control registers into %ecr_
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and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Daniel Dunbar
a5d0b54ec1
MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since
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we don't currently support relaxing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:34:01 +00:00
Dan Gohman
34dcc6fadc
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
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doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1
Add a missing break statement to fix unintentional fall-through
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(replacing the previous patch for the same issue).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 05:08:57 +00:00
Eric Christopher
f865cb5c1f
Revert r103156 since it was breaking the build bots.
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Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 02:29:06 +00:00
Evan Cheng
9c35ee2099
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:54:03 +00:00
Evan Cheng
4ffc22ae00
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:52:03 +00:00
Evan Cheng
d31c5496d7
Cosmetic changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:34:11 +00:00
Evan Cheng
7f2f436267
storeRegToStackSlot has forgotten about QPR_8 register class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 01:32:54 +00:00
Jim Grosbach
29402132f3
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
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instructions to subtarget features and update tests to reflect.
PR5717.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 23:44:43 +00:00
Sean Callanan
be192dd1e9
Fixed a sign-extension bug in the X86 disassembler
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that was causing PC-relative branch targets to be
evaluated incorrectly. Also added support for
checking operand values to the llvm-mc tester.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 22:47:27 +00:00
Evan Cheng
676b2dfd27
Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 22:15:40 +00:00
Dan Gohman
9f2cda73e4
No-ops emitted for scheduling don't correspond with anything in the
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user's source, so don't arbitrarily assign them a debug location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:58:01 +00:00
Jim Grosbach
b1dc393bd5
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
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Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 18:28:36 +00:00
Evan Cheng
d2c2d1809f
Trim include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103103 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 18:27:57 +00:00
Eric Christopher
f4f06906b8
Revert 102941, we're going to do this via attr and can just
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hack the code to turn it off when debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 07:35:59 +00:00
Eric Christopher
d2760d1cba
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 22:13:03 +00:00
Evan Cheng
94cc6d3a2b
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:39:49 +00:00
Evan Cheng
826bdfa603
Do not pre-allocate for registers which form a REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:38:12 +00:00
Chris Lattner
d4ac35b350
"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."
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Patch by Kalle Raiskila!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 17:58:46 +00:00
Daniel Dunbar
e9f0fb4179
MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of
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instructions which have no direct register usage.
Darwin 'as' accepts:
add $0, (%rax)
but rejects
mov $0, (%rax)
for example.
Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103015 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 17:31:02 +00:00
Daniel Dunbar
c918d6043b
MC/X86: Add "support" for matching ATT style mnemonic prefixes.
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- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 16:12:42 +00:00
Gabor Greif
2f256f4561
fix operand indexes when outputting InvokeInsts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103003 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 09:23:54 +00:00