Commit Graph

70 Commits

Author SHA1 Message Date
1b40b342eb Use range-based for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-13 05:12:19 +00:00
2895d9527d Reduce code duplication a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-27 05:26:42 +00:00
00bc445d75 Fix TableGen -gen-disassembler output for bit fields with an offset.
This fixes bit assignments like this
Inst{7-0} = Foo{9-2}

Patch by Steve King.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218560 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-27 04:38:02 +00:00
7125897c92 Use vector constructor instead of a for loop to initialize entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217123 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-04 04:49:03 +00:00
8f2394e5af Fix ambiguous call to make_unique and clang-format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217023 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 08:22:30 +00:00
732b026119 Recommit "Use unique_ptr to manager FilterChooser ownership."
Just using insert of a pair this time instead of emplace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217018 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 06:07:54 +00:00
6426140b90 Revert "Use unique_ptr to manager FilterChooser ownership."
std::map::emplace isn't working on some of the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217015 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 05:59:23 +00:00
e2d40936f6 Use unique_ptr to manager FilterChooser ownership.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217014 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 05:49:09 +00:00
5c581578ff Implement move constructor and remove copy constructor for Filter objects in FixedLenDecoderEmitter. Also remove unused copy constructor of FilterChooser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217013 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 05:49:07 +00:00
915c29c11c [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, TableGen edition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206846 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 03:06:00 +00:00
095734c578 [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 07:20:03 +00:00
79c15b23c9 [TableGen] Optionally forbid overlap between named and positional operands
There are currently two schemes for mapping instruction operands to
instruction-format variables for generating the instruction encoders and
decoders for the assembler and disassembler respectively: a) to map by name and
b) to map by position.

In the long run, we'd like to remove the position-based scheme and use only
name-based mapping. Unfortunately, the name-based scheme currently cannot deal
with complex operands (those with suboperands), and so we currently must use
the position-based scheme for those. On the other hand, the position-based
scheme cannot deal with (register) variables that are split into multiple
ranges. An upcoming commit to the PowerPC backend (adding VSX support) will
require this capability. While we could teach the position-based scheme to
handle that, since we'd like to move away from the position-based mapping
generally, it seems silly to teach it new tricks now. What makes more sense is
to allow for partial transitioning: use the name-based mapping when possible,
and only use the position-based scheme when necessary.

Now the problem is that mixing the two sensibly was not possible: the
position-based mapping would map based on position, but would not skip those
variables that were mapped by name. Instead, the two sets of assignments would
overlap. However, I cannot currently change the current behavior, because there
are some backends that rely on it [I think mistakenly, but I'll send a message
to llvmdev about that]. So I've added a new TableGen bit variable:
noNamedPositionallyEncodedOperands, that can be used to cause the
position-based mapping to skip variables mapped by name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203767 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:57:54 +00:00
a01427c15a Remove unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201041 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-09 07:55:19 +00:00
426497e2fb Remove some unnecessary code. The conditions it was checking had already been ruled out by the caller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201039 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-09 07:13:41 +00:00
d715c3e9ac Add support for positionally-encoded operands to FixedLenDecoderEmitter
Unfortunately, the PowerPC instruction definitions make heavy use of the
positional operand encoding heuristic to map operands onto bitfield variables
in the instruction definitions. Changing this to use name-based mapping is not
trivial, however, because additional infrastructure needs to be designed to
handle mapping of complex operands (with multiple suboperands) onto multiple
bitfield variables.

In the mean time, this adds support for positionally encoded operands to
FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC
backend. To prevent an accidental reliance on this feature, and to prevent an
undesirable interaction with existing disassemblers, a backend must opt-in to
this support by setting the new decodePositionallyEncodedOperands
instruction-set bit to true.

When enabled, this iterates the variables that contribute to the instruction
encoding, just as the encoder does, and emulates the procedure the encoder uses
to map "numbered" operands to variables. The bit range for each variable is
also determined as the encoder determines them. This map is then consulted
during the decoder-generator's loop over operands to decode, allowing the
decoder to understand both position-based and name-based operand-to-variable
mappings.

As noted in the comment on the decodePositionallyEncodedOperands definition,
this support should be removed once it is no longer needed. There should be no
change to existing disassemblers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:12:53 +00:00
e14ad8538f Add support for PointerLikeRegClass to FixedLenDecoderEmitter
This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter
should recognize PointerLikeRegClass operands as register types, and generate
register-like decoding calls instead of treating them like immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 14:58:22 +00:00
af73dfe6f1 Support little-endian encodings in the FixedLenDecoderEmitter
The convention used to specify the PowerPC ISA is that bits are numbered in
reverse order (0 is the index of the high bit). To support this "little endian"
encoding convention, CodeEmitterGen will reverse the bit numberings prior to
generating the encoding tables. In order to generate a disassembler,
FixedLenDecoderEmitter needs to do the same.

This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget
(where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This
is prep work for disassembly support in the PPC backend (which is the only
in-tree user of this little-endian encoding support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-17 22:37:50 +00:00
8819c84aed Remove several unused variables.
Patch by Alp Toker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 13:32:03 +00:00
54911a5303 Teaching llvm-tblgen to not emit a switch statement when there are no case statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-15 16:53:32 +00:00
fc093def2d TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction().
Reported by Yang Yongyong, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 06:43:14 +00:00
4ffd89fa4d Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 10:37:14 +00:00
61131ab15f Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 20:33:17 +00:00
3f7b7f8ce0 tblgen: Use semantically correct RTTI functions.
Also, some minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:24:47 +00:00
6cfc806a6b tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:24:43 +00:00
736ceace11 tblgen: Replace uses of dynamic_cast<XXXRecTy> with dyn_cast<>.
This is a mechanical change of dynamic_cast<> to dyn_cast<>. A number of
these uses are actually more like isa<> or cast<>, and will be changed
to the semanticaly appropriate one in a future patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05 03:31:58 +00:00
9bb938c540 TableGen: Add initializer.
Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 18:00:53 +00:00
307525cd24 Re-work bit/bits value resolving in tblgen
- This patch is inspired by the failure of the following code snippet
  which is used to convert enumerable values into encoding bits to
  improve the readability of td files.

  class S<int s> {
    bits<2> V = !if(!eq(s, 8),  {0, 0},
                !if(!eq(s, 16), {0, 1},
                !if(!eq(s, 32), {1, 0},
                !if(!eq(s, 64), {1, 1}, {?, ?}))));
  }

  Later, PR8330 is found to report not exactly the same bug relevant
  issue to bit/bits values.

- Instead of resolving bit/bits values separately through
  resolveBitReference(), this patch adds getBit() for all Inits and
  resolves bit value by resolving plus getting the specified bit. This
  unifies the resolving of bit with other values and removes redundant
  logic for resolving bit only. In addition,
  BitsInit::resolveReferences() is optimized to take advantage of this
  origanization by resolving VarBitInit's variable reference first and
  then getting bits from it.

- The type interference in '!if' operator is revised to support possible
  combinations of int and bits/bit in MHS and RHS.

- As there may be illegal assignments from integer value to bit, says
  assign 2 to a bit, but we only check this during instantiation in some
  cases, e.g.

  bit V = !if(!eq(x, 17), 0, 2);

  Verbose diagnostic message is generated when invalid value is
  resolveed to help locating the error.

- PR8330 is fixed as well.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 23:32:48 +00:00
8cd9eaef01 Declare some for loop indices inside the for loop statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162085 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 05:42:16 +00:00
c056483fc6 Fix up indentation of outputted decode function for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 05:16:15 +00:00
95d235ddb6 Fix a const violation in the generated disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161940 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15 10:26:44 +00:00
fc1a161d76 Switch the fixed-length disassembler to be table-driven.
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
  Previous: 35.5s
  New:       8.9s

TEXT size:
  Previous: 447,251
  New:      297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14 19:06:05 +00:00
6f36fa981a Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11 15:37:55 +00:00
545b962f15 Second part for the 153874 one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02 15:46:46 +00:00
5a4c790c06 More const-correcting of FixedLenDecoderEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152906 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 06:52:56 +00:00
eb5cd61070 Const-correct the FixedLenDecoderEmitter. Pass a few things by const reference instead of value to avoid some copying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 05:58:09 +00:00
d936045625 Spacing fixes. Mostly aligning arguments that spilled onto next line with the opening parenthese instead of 2 spaces in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152889 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 01:19:24 +00:00
797ba55e20 Remove unused field NumVariable from Filter class. Even it was needed the same result could be found with VariableInstructions.size(). Also fix some typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 00:56:01 +00:00
c007ba86f3 Remove unused field from FixedLenDecoderEmitter. Move NumberedInstructions declaration from class to run method since its only used there and was being reinitialized anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 06:39:00 +00:00
9c826d2d3c Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 22:07:56 +00:00
3015dfb7d7 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 10:56:31 +00:00
655b8de7b2 Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 07:21:30 +00:00
684dfcf724 Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 16:56:47 +00:00
7c78888887 Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 16:41:13 +00:00
1cea66c3ba Subtarget getFeatureBits() returns a uint64_t, not unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 02:47:54 +00:00
64a17b309d Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:00:31 +00:00
0d76b19919 Fix warning on windows; use of comparison with bool argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:12:01 +00:00
22b4c819d4 Fix a use of freed string contents.
Speculatively try to fix our windows testers with a patch I found on the internet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139279 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 05:25:49 +00:00
ed968a9a04 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 05:23:14 +00:00
a5d5856854 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:42:28 +00:00
83e3f67fb6 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 17:44:15 +00:00