6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-27 13:30:05 +00:00
Code Issues Projects Releases Wiki Activity
72,965 Commits 39 Branches 0 Tags 277 MiB
25255cbe00
Commit Graph

7139 Commits

Author SHA1 Message Date
Eli Friedman
25255cbe00 Add full x86 fast-isel support for memcpy and memset. 
rdar://9431466



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 23:39:36 +00:00
Eli Friedman
be5cbaa627 PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 01:13:01 +00:00
Eli Friedman
6ad0468149 Chris fixed this README a while back by changing how clang generates code for structs like the given struct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132815 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 23:02:19 +00:00
Eli Friedman
6f19c67d84 Revert 132789; it breaks tests. My mistake. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 19:33:30 +00:00
Eli Friedman
aebc3c1610 Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132789 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 18:55:00 +00:00
Jakob Stoklund Olesen
2a9d1ca9c2 Remove custom allocation order boilerplate that is no longer needed. 
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 16:56:59 +00:00
Eric Christopher
471e422480 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-08 23:55:35 +00:00
Stuart Hastings
f99a4b82a4 Followup to 132458, omit unnecessary stack copy when x87 input is a 
load.  rdar://problem/6373334


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-06 23:15:58 +00:00
Stuart Hastings
865f09334f Reapply 132424 with fixes. This fixes PR10068. 
rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 23:53:54 +00:00
Eric Christopher
100c833416 Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen
4f3fb6d08b Flag unallocatable register classes instead of giving them empty 
allocation orders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:07:24 +00:00
Rafael Espindola
251b4a0405 Revert 132424 to fix PR10068. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 19:57:47 +00:00
Stuart Hastings
84be958ed8 Omit unnecessary stack copy when x87 input is a load. 
rdar://problem/6373334


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 15:57:11 +00:00
Jakob Stoklund Olesen
fa226bccaa Use TRI::has{Sub,Super}ClassEq() where possible. 
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 05:43:46 +00:00
Rafael Espindola
cde4ce411b Don't hardcode the %reg format in the streamer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 02:34:55 +00:00
Stuart Hastings
ec880283b3 Recommit 132404 with fixes. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 21:33:14 +00:00
Stuart Hastings
4abc5fea9c Revert 132404 to appease a buildbot. rdar://problem/5993888 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132419 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 19:52:20 +00:00
Stuart Hastings
10ff0bbdfb Add support for x86 CMPEQSS and friends. These instructions do a 
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 17:17:45 +00:00
Jakob Stoklund Olesen
1f9a09c614 Fix PR10059 and future variations by handling all register subclasses. 
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 15:32:10 +00:00
Stuart Hastings
4fd0dee3bf FGETSIGN support for x86, using movmskps/pd. Will be enabled with a 
patch to TargetLowering.cpp.  rdar://problem/5660695


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 04:39:42 +00:00
Rafael Espindola
6e032942cf Use the dwarf->llvm mapping to print register names in the cfi 
directives.

Fixes PR9826.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-30 20:20:15 +00:00
Rafael Espindola
7a067cc6e0 Introduce the DwarfRegAlias class for declaring that two registers have the 
same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-30 17:49:59 +00:00
Rafael Espindola
e99f75a300 Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they are 
subregisters of the 64 bit ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-30 16:04:54 +00:00
Rafael Espindola
36ea4f0206 Add 132187 back now that the real problem is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 00:24:37 +00:00
Rafael Espindola
157371f376 It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132230 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 23:36:02 +00:00
Cameron Zwarich
f5e771db37 Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass() 
was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132225 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 22:26:04 +00:00
Jakob Stoklund Olesen
11f6cc96bf Delete MethodBodies that only filtered reserved registers. 
The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 18:27:13 +00:00
Rafael Espindola
81e193cc1f Remove dwarf numbers from subregs. We should use DW_OP_bit_piece to 
refer to them.

I tested this with both check-all and the gdb testsuite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132187 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 15:08:24 +00:00
Chad Rosier
62660310d9 Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. 
crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 23:13:19 +00:00
Stuart Hastings
2aa0f23e1c Reverting 132105: it broke some LLVM-GCC DejaGNU tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 04:09:49 +00:00
Stuart Hastings
aa4e6afc9b Correctly handle a one-word struct passed byval on x86_64. 
rdar://problem/6920088


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 02:44:56 +00:00
Eli Friedman
76927d7303 Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent. 
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 23:49:02 +00:00
Francois Pichet
1b47720391 Remove unused OpcodeMask enumerator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 17:02:53 +00:00
Francois Pichet
d9e57c146d Fix MSVC warning: "is out of range for enum constant" 
MSVC doesn't support 64 bit enum. 
OpcodeMask is not used anywhere in the code base.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 15:58:10 +00:00
Rafael Espindola
fc2bb8c444 Replace the -unwind-tables option with a per function flag. This is more 
LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132033 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 03:44:17 +00:00
Charles Davis
6b918b8466 Add a method to TargetRegisterInfo to get the register number that the Win64 EH 
scheme uses internally. Implement it for x86 (the only architecture that LLVM
supports for which this matters right now).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 16:57:53 +00:00
Evan Cheng
b5a55d979c - Teach SelectionDAG::isKnownNeverZero to return true (op x, c) when c is 
non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
  when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.

rdar://9490949


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 01:48:22 +00:00
Chris Lattner
92f920c109 add a missing alias to make us more bug compatible with gcc, PR9378 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131874 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-22 22:31:57 +00:00
Benjamin Kramer
b22da2a72c X86: smulo -> add is now done target-independently in DAGCombiner, remove the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131801 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-21 18:32:01 +00:00
Cameron Zwarich
37fed38ec1 Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC code. It 
is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-21 04:13:49 +00:00
Eli Friedman
c088345f13 Add fast-isel support for byval calls on x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131764 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 22:21:04 +00:00
Stuart Hastings
0e29ed081b Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends. 
rdar://problem/8614450


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 19:04:40 +00:00
Benjamin Kramer
eb274e6bdd Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 15:11:26 +00:00
Chad Rosier
a166089f36 Don't attempt to tail call optimize for Win64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 00:59:28 +00:00
Evan Cheng
2e6496026f Revert r131664 and fix it in instcombine instead. rdar://9467055 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 00:54:37 +00:00
Eli Friedman
dc51575a5f Add fast-isel support for zeroext and signext ret instructions on x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 22:16:13 +00:00
Eric Christopher
2bbecd8f6d Oddly people want to use the 'r' constraint for fp constants on x86. 
Fixes rdar://9218925
Fixes PR9601


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 21:33:47 +00:00
Rafael Espindola
a3bff99f0a ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S. 
Fixes PR9934.

We really need to start tblgening the relocation info :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 20:32:34 +00:00
Evan Cheng
0efaa5e6a1 crc32 with 64-bit output zeros upper 32-bits. rdar://9467055 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131664 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 18:57:12 +00:00
Stuart Hastings
d22f036c2a Reverting 131641 to investigate 'bot complaint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 17:54:42 +00:00