Commit Graph

101587 Commits

Author SHA1 Message Date
Justin Bogner
2563e201c1 Support: Document Endian.h functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204671 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 21:30:55 +00:00
David Blaikie
f4ec1889db DebugInfo: Implement relative addressing for DW_AT_ranges under fission
This removes the debug_ranges relocations from debug_info.dwo (but
doesn't implement the DW_AT_GNU_ranges_base which is also necessary for
correct functioning)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204668 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 21:07:27 +00:00
David Blaikie
05e62b507a DebugInfo: Don't emit relocations to abbreviations in debug_info.dwo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204667 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:53:02 +00:00
David Blaikie
f2c696ac66 DwarfDebug: Remove an unused parameter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204665 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:31:01 +00:00
Matt Arsenault
e130844e41 R600: Don't viewCFG() under DEBUG() except on failure.
Having these popping up every time you use -debug is really
irritating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:29:02 +00:00
David Blaikie
fcd547ce03 Remove unused parameter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204663 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:28:10 +00:00
Matt Arsenault
add2e2ec8f R600/SI: Fix extra mov from legalizing 64-bit SALU ops.
Check the register class of each operand individually
to avoid an extra copy to a vgpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:08:13 +00:00
Matt Arsenault
3a96e61469 R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.
No longer asserts, but now you get moves loading legal immediates
into the split 32-bit operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204661 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:08:09 +00:00
Matt Arsenault
db1807144a R600/SI: Fix 64-bit bit ops that require the VALU.
Try to match scalar and first like the other instructions.
Expand 64-bit ands to a pair of 32-bit ands since that is not
available on the VALU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:08:05 +00:00
Yaron Keren
d816eda3c7 In Release modes, Visual Studio complains that the Operator destructor in User.cpp
never returns, which is true by design. 

Initially assumed that the reason is llvm_unreachable being dependent on NDEBUG.

However, even if llvm_unreachable is replaced by __assume(false), VC still warns in
Release modes but not in Debug modes...

The real reason turned out to be optimization flags.
With /Od in Debug modes the warning is not issued whereas with /O1 it is.

I could not find any documentation to this effect, but it is reproducable:

Try compiling http://msdn.microsoft.com/en-us/library/khwfyc5d(v=vs.90).aspx
with /O1 and then with /Od.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 19:48:13 +00:00
Matt Arsenault
6c199d8212 R600: Implement isNarrowingProfitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 19:43:31 +00:00
Matt Arsenault
03cd663eb1 R600/SI: Move splitting 64-bit immediates to separate function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204651 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 18:26:52 +00:00
Aaron Ballman
9f00cd9602 Adding some very nascent information about the clang tablegen backends, with a promise to add more information later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 18:18:31 +00:00
Ulrich Weigand
47eac58333 [PowerPC] Generate little-endian object files
As a first step towards real little-endian code generation, this patch
changes the PowerPC MC layer to actually generate little-endian object
files.  This involves passing the little-endian flag through the various
layers, including down to createELFObjectWriter so we actually get basic
little-endian ELF objects, emitting instructions in little-endian order,
and handling fixups and relocations as appropriate for little-endian.

The bulk of the patch is to update most test cases in test/MC/PowerPC
to verify both big- and little-endian encodings.  (The only test cases
*not* updated are those that create actual big-endian ABI code, like
the TLS tests.)

Note that while the object files are now little-endian, the generated
code itself is not yet updated, in particular, it still does not adhere
to the ELFv2 ABI.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 18:16:09 +00:00
Quentin Colombet
4768df00c4 [X86][ISelDAG] Add missing fallback patterns for avx2 broadcast instructions.
Those patterns are used when the load cannot be folded into the related broadcast
during the select phase.
This happens when the load gets additional uses that were not anticipated during
the previous lowering phases (constant vector to constant load, then constant
load reused) or when selection DAG is not able to prove that folding the load
will not create a cycle in the DAG.

<rdar://problem/16074331>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204631 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 17:54:19 +00:00
Matt Arsenault
875870fdb4 R600/SI: Fix 64-bit private loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204630 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 17:50:46 +00:00
Hans Wennborg
657c472bb0 VS integration installer: set SUCCESS=1 if we find VS 2013
Previously we would print an error message on machines where the only VS
version we find is 2013, even though we successfully install the integration
files for it.

Also, we shouldn't have two END labels.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204629 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 17:33:22 +00:00
Eli Bendersky
b6f02c13da Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.
Make sure such IR gets properly lowered to PTX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:52:30 +00:00
Adam Nemet
a1b54dd1ff [X86] Fix non-determinism in LowerVectorAllZeroTest
This can be observed with the old testcase of CodeGen/X86/pr12312.ll:

47c47
<       vorps   %ymm0, %ymm1, %ymm0
---
>       vorps   %ymm1, %ymm0, %ymm0
97c97
<       vorps   %ymm1, %ymm0, %ymm0
---
>       vorps   %ymm0, %ymm1, %ymm0

The vector VecIns is populated with all the values from VecInMap. This is done
while iterating VecInMap.  VecInMap uses a hash of pointer values so the
resulting order can vary depending on the memory layout.

The fix is to populate the vector VecIns earlier as VecInMap is populated.
This is done in DAG traversal order.

Fixes <rdar://problem/16398806>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204623 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:52:08 +00:00
Daniel Sanders
8ce101ed10 [mips] Add error message when trying to use $at in '.set noat' mode.
Summary:
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3158

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:48:01 +00:00
Eli Bendersky
2685aa8713 Removes the NVPTXSplitBBatBar pass.
This pass is a historic remnant and actually causes less efficient code to be
generated in some cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204620 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:36:39 +00:00
Tom Stellard
4ddee6a5da R600/SI: Fix warning with gcc 4.8.2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:12:34 +00:00
Tom Stellard
65b5e9b4ef R600/SI: Promote fp64 SELECT to i64
This type promotion is replacing a Tablegen pattern and it is already
covered by existing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204617 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:07:30 +00:00
Tom Stellard
b15ac1b99b SelectionDAG: Allow promotion of SELECT nodes from float to int types
And vice-versa, as long as the types are the same width.

There are a few R600 tests that will cover this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:07:28 +00:00
Tom Stellard
9958475129 R600: Reorganize tablegen instruction definitions
Each GPU family now has its own file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:07:25 +00:00
Will Schmidt
04c252cc93 [PPC64LE] ELFv2 ABI updates for the .opd section
[PPC64LE] ELFv2 ABI updates for the .opd section
The PPC64 Little Endian (PPC64LE) target supports the ELFv2 ABI, and as
such, does not have a ".opd" section.  This is keyed off a _CALL_ELF=2
macro check.

The CALL_ELF check is not clearly documented at this time.  The basis
for usage in this patch is from the gcc thread here:
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg01144.html

> Adding comment from Uli:
Looks good to me.  I think the old-style JIT doesn't really work
anyway for 64-bit, but at least with this patch LLVM will compile
and link again on a ppc64le host ...




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:04:15 +00:00
Daniel Sanders
75002071fd [mips] Add regression tests for parenthetic expressions in MIPS assembly.
Summary:
These expressions already worked but weren't tested.

Patch by Robert N. M. Watson and David Chisnall (it was originally two patches)
Their work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 15:42:21 +00:00
Daniel Sanders
eaae583095 [mips] Allow dsubu to take an immediate as an alias for dsubiu.
Summary:
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3155

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204611 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 15:38:00 +00:00
Hal Finkel
38a80e9b21 [PowerPC] Mark many instructions as commutative
I'm under the impression that we used to infer the isCommutable flag from the
instruction-associated pattern. Regardless, we don't seem to do this (at least
by default) any more. I've gone through all of our instruction definitions, and
marked as commutative all of those that should be trivial to commute (by
exchanging the first two operands). There has been special code for the RL*
instructions, and that's not changed.

Before this change, we had the following commutative instructions:

 RLDIMI
 RLDIMIo
 RLWIMI
 RLWIMI8
 RLWIMI8o
 RLWIMIo
 XSADDDP
 XSMULDP
 XVADDDP
 XVADDSP
 XVMULDP
 XVMULSP

After:

 ADD4
 ADD4o
 ADD8
 ADD8o
 ADDC
 ADDC8
 ADDC8o
 ADDCo
 ADDE
 ADDE8
 ADDE8o
 ADDEo
 AND
 AND8
 AND8o
 ANDo
 CRAND
 CREQV
 CRNAND
 CRNOR
 CROR
 CRXOR
 EQV
 EQV8
 EQV8o
 EQVo
 FADD
 FADDS
 FADDSo
 FADDo
 FMADD
 FMADDS
 FMADDSo
 FMADDo
 FMSUB
 FMSUBS
 FMSUBSo
 FMSUBo
 FMUL
 FMULS
 FMULSo
 FMULo
 FNMADD
 FNMADDS
 FNMADDSo
 FNMADDo
 FNMSUB
 FNMSUBS
 FNMSUBSo
 FNMSUBo
 MULHD
 MULHDU
 MULHDUo
 MULHDo
 MULHW
 MULHWU
 MULHWUo
 MULHWo
 MULLD
 MULLDo
 MULLW
 MULLWo
 NAND
 NAND8
 NAND8o
 NANDo
 NOR
 NOR8
 NOR8o
 NORo
 OR
 OR8
 OR8o
 ORo
 RLDIMI
 RLDIMIo
 RLWIMI
 RLWIMI8
 RLWIMI8o
 RLWIMIo
 VADDCUW
 VADDFP
 VADDSBS
 VADDSHS
 VADDSWS
 VADDUBM
 VADDUBS
 VADDUHM
 VADDUHS
 VADDUWM
 VADDUWS
 VAND
 VAVGSB
 VAVGSH
 VAVGSW
 VAVGUB
 VAVGUH
 VAVGUW
 VMADDFP
 VMAXFP
 VMAXSB
 VMAXSH
 VMAXSW
 VMAXUB
 VMAXUH
 VMAXUW
 VMHADDSHS
 VMHRADDSHS
 VMINFP
 VMINSB
 VMINSH
 VMINSW
 VMINUB
 VMINUH
 VMINUW
 VMLADDUHM
 VMULESB
 VMULESH
 VMULEUB
 VMULEUH
 VMULOSB
 VMULOSH
 VMULOUB
 VMULOUH
 VNMSUBFP
 VOR
 VXOR
 XOR
 XOR8
 XOR8o
 XORo
 XSADDDP
 XSMADDADP
 XSMAXDP
 XSMINDP
 XSMSUBADP
 XSMULDP
 XSNMADDADP
 XSNMSUBADP
 XVADDDP
 XVADDSP
 XVMADDADP
 XVMADDASP
 XVMAXDP
 XVMAXSP
 XVMINDP
 XVMINSP
 XVMSUBADP
 XVMSUBASP
 XVMULDP
 XVMULSP
 XVNMADDADP
 XVNMADDASP
 XVNMSUBADP
 XVNMSUBASP
 XXLAND
 XXLNOR
 XXLOR
 XXLXOR

This is a by-inspection change, and I'm not sure how to write a reliable test
case. I would like advice on this, however.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204609 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 15:07:28 +00:00
Daniel Sanders
67db74e02c [mips] Implement shorthand add / sub forms for MIPS.
Summary:
- If only two registers are passed to a three-register operation, then the
  first argument is both source and destination register.

- If a non-register is passed as the last argument, generate the immediate
  version of the instruction.

Also mark DADD commutative and add scheduling information (to the generic
scheduler), and implement DSUB.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

CC: theraven

Differential Revision: http://llvm-reviews.chandlerc.com/D3148

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 14:05:39 +00:00
Justin Holewinski
b8cb709858 [NVPTX] Add isel patterns for addrspacecast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204600 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 11:17:53 +00:00
Renato Golin
72270aabf7 Update release notes with EHABI current behaviour
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204598 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 11:02:38 +00:00
Hal Finkel
2393d22ca4 [PowerPC] Don't schedule VSX copy legalization unless VSX is enabled
There is no need to schedule this extra pass if it will have nothing to do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204594 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 09:51:41 +00:00
Hal Finkel
72448143b5 [PowerPC] Update comment re: VSX copy-instruction selection
I've done some experimentation with this, and it looks like using the
lower-latency (but lower throughput) copy instruction is essentially always the
right thing to do.

My assumption is that, in order to be relatively sure that the higher-latency
copy will increase throughput, we'd want to have it unlikely to be in-flight
with its use. On the P7, the global completion table (GCT) can hold a maximum
of 120 instructions, shared among all active threads (up to 4), giving 30
instructions per thread.  So specifically, I'd require at least that many
instructions between the copy and the use before the high-latency variant is
used.

Trying this, however, over the entire test suite resulted in zero cases where
the high-latency form would be preferable. This may be a consequence of the
fact that the scheduler views copies as free, and so they tend to end up close
to their uses. For this experiment I created a function:

  unsigned chooseVSXCopy(MachineBasicBlock &MBB,
                         MachineBasicBlock::iterator I,
                         unsigned DestReg, unsigned SrcReg,
                         unsigned StartDist = 1,
                         unsigned Depth = 3) const;

with an implementation like:

  if (!Depth)
    return PPC::XXLOR;

  const unsigned MaxDist = 30;
  unsigned Dist = StartDist;
  for (auto J = I, JE = MBB.end(); J != JE && Dist <= MaxDist; ++J) {
    if (J->isTransient() && !J->isCopy())
      continue;

    if (J->isCall() || J->isReturn() || J->readsRegister(DestReg, TRI))
      return PPC::XXLOR;

    ++Dist;
  }

  // We've exceeded the required distance for the high-latency form, use it.
  if (Dist > MaxDist)
    return PPC::XVCPSGNDP;

  // If this is only an exit block, use the low-latency form.
  if (MBB.succ_empty())
    return PPC::XXLOR;

  // We've reached the end of the block, check the successor blocks (up to some
  // depth), and use the high-latency form if that is okay with all successors.
  for (auto J = MBB.succ_begin(), JE = MBB.succ_end(); J != JE; ++J) {
    if (chooseVSXCopy(**J, (*J)->begin(), DestReg, SrcReg,
                      Dist, --Depth) == PPC::XXLOR)
      return PPC::XXLOR;
  }

  // All of our successor blocks seem okay with the high-latency variant, so
  // we'll use it.
  return PPC::XVCPSGNDP;

and then changed the copy opcode selection from:
    Opc = PPC::XXLOR;
to:
    Opc = chooseVSXCopy(MBB, std::next(I), DestReg, SrcReg);

In conclusion, I'm removing the FIXME from the comment, because I believe that
there is, at least absent other examples, nothing to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204591 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 09:36:36 +00:00
Rafael Espindola
2236f9348d Teach llvm-readobj to print human friendly description of reserved sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 05:00:34 +00:00
Karthik Bhat
07707e8969 Allow constant folding of ceil function whenever feasible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 04:36:06 +00:00
Rafael Espindola
0259b8e14f Add back tests that were reverted in r204203.
They pass again with the fix in r204581.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 03:48:15 +00:00
Rafael Espindola
0bce3343cc Propagate section from base to derived symbol.
We were already propagating the section in

a = b

With this patch we also propagate it for

a = b + 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 03:43:21 +00:00
Duncan P. N. Exon Smith
b83e788db5 InstrProf: Silence spurious warnings in GCC 4.8
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204580 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 00:47:18 +00:00
NAKAMURA Takumi
12da52f917 SupportTests.LockFileManagerTest: Add assertions for Win32.
- create_link doesn't work for nonexistent file.
  - remove cannot remove working directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204579 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 23:55:57 +00:00
Arnaud A. de Grandmaison
b0c513b9ba ARM: no need to update SplatBits as it is not used
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204575 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 21:14:32 +00:00
Justin Bogner
f5afb78a9d llvm-profdata: Check for bad data in the show command
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204573 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 20:55:53 +00:00
Justin Bogner
5ecdfc1004 llvm-profdata: Use Format.h instead of handrolling a formatter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204571 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 20:43:50 +00:00
David Majnemer
77df5169a8 WinCOFF: Add support for -ffunction-sections
This is a pretty straight forward translation for COFF, we just need to
stick the function in a COMDAT section marked as
IMAGE_COMDAT_SELECT_NODUPLICATES.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204565 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 17:47:39 +00:00
Nuno Lopes
2ca626570f remove a bunch of unused private methods
found with a smarter version of -Wunused-member-function that I'm playwing with.
Appologies in advance if I removed someone's WIP code.

 include/llvm/CodeGen/MachineSSAUpdater.h            |    1 
 include/llvm/IR/DebugInfo.h                         |    3 
 lib/CodeGen/MachineSSAUpdater.cpp                   |   10 --
 lib/CodeGen/PostRASchedulerList.cpp                 |    1 
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp    |   10 --
 lib/IR/DebugInfo.cpp                                |   12 --
 lib/MC/MCAsmStreamer.cpp                            |    2 
 lib/Support/YAMLParser.cpp                          |   39 ---------
 lib/TableGen/TGParser.cpp                           |   16 ---
 lib/TableGen/TGParser.h                             |    1 
 lib/Target/AArch64/AArch64TargetTransformInfo.cpp   |    9 --
 lib/Target/ARM/ARMCodeEmitter.cpp                   |   12 --
 lib/Target/ARM/ARMFastISel.cpp                      |   84 --------------------
 lib/Target/Mips/MipsCodeEmitter.cpp                 |   11 --
 lib/Target/Mips/MipsConstantIslandPass.cpp          |   12 --
 lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp              |   21 -----
 lib/Target/NVPTX/NVPTXISelDAGToDAG.h                |    2 
 lib/Target/PowerPC/PPCFastISel.cpp                  |    1 
 lib/Transforms/Instrumentation/AddressSanitizer.cpp |    2 
 lib/Transforms/Instrumentation/BoundsChecking.cpp   |    2 
 lib/Transforms/Instrumentation/MemorySanitizer.cpp  |    1 
 lib/Transforms/Scalar/LoopIdiomRecognize.cpp        |    8 -
 lib/Transforms/Scalar/SCCP.cpp                      |    1 
 utils/TableGen/CodeEmitterGen.cpp                   |    2 
 24 files changed, 2 insertions(+), 261 deletions(-)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204560 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 17:09:26 +00:00
Hal Finkel
b6cbecd272 [PowerPC] Make use of VSX f64 <-> i64 conversion instructions
When VSX is available, these instructions should be used in preference to the
older variants that only have access to the scalar floating-point registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 05:35:00 +00:00
Lang Hames
fb51aac129 Revert r204076 for now - it caused significant regressions in a number of
benchmarks.

<rdar://problem/16368461>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 04:22:31 +00:00
Duncan P. N. Exon Smith
0695b20d9a InstrProf: Check pointer size in raw profile
Since the profile can come from 32-bit machines, we need to check the
pointer size.  Change the magic number to facilitate this.

Adds tests for reading 32-bit and 64-bit binaries (both big- and
little-endian).  The tests write a binary using printf in RUN lines
(like raw-magic-but-no-header.test).  Assuming the bots don't complain,
this seems like a better way forward for testing RawInstrProfReader than
committing binary files.

<rdar://problem/16400648>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204557 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 03:38:12 +00:00
Rafael Espindola
4ff2dadebe Propagate types from symbol to aliases.
This is similar, but not identical to what gas does. The logic in MC is to just
compute the symbol table after parsing the entire file. GAS is mixed, given

.type b, @object
a = b
b:
.type b, @function

It will propagate the change and make 'a' a function. Given

.type b, @object
b:
a = b
.type b, @function

the type of 'a' is still object.

Since we do the computation in the end, we produce a function in both cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204555 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 03:33:20 +00:00
NAKAMURA Takumi
c8ca83201c [CMake] LLVMProfileData: No need to add LINK_LIBS here. LLVMBuild should do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204553 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-23 01:23:36 +00:00