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29 Commits

Author SHA1 Message Date
Akira Hatanaka
77e1ebd18f [mips] Set instruction itineraries of loads, stores and conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:28:24 +00:00
Vladimir Medic
bf7f7b5e0e This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:41:17 +00:00
Akira Hatanaka
1e09ed1389 [mips] Fix instruction definitions that were incorrectly marked as code-gen-only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188690 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-19 19:08:03 +00:00
Akira Hatanaka
491d04969d [mips] Rename accumulator register classes and FP register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-08 21:54:26 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:08:38 +00:00
Akira Hatanaka
6b034bb3ae [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of 
instructions defined in MipsInstrInfo.td as codegen-only instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187828 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 23:01:10 +00:00
Akira Hatanaka
52b7321a48 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 00:55:34 +00:00
Vladimir Medic
b67775df0c This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-30 10:12:14 +00:00
Akira Hatanaka
407883b69b [mips] Fix FP conditional move instructions to have explicit FP condition code 
register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 20:51:20 +00:00
Akira Hatanaka
9955cb931b [mips] Fix floating point branch, comparison, and conditional move instructions 
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187233 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 19:01:56 +00:00
Vladimir Medic
0884836277 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186397 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-16 10:07:14 +00:00
Akira Hatanaka
ee767fe2d2 [mips] Fix inefficient code generation. 
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:

(select (setgt a, Constant), T, F)

The pattern above effectively turns into this:

(conditional-move (setlt a, Constant + 1), F, T)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176384 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-01 21:52:08 +00:00
Akira Hatanaka
079a0ff196 Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176380 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-01 21:22:21 +00:00
Akira Hatanaka
63723e5bf8 [mips] Refactor conditional move instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171511 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-04 19:16:38 +00:00
Akira Hatanaka
c567b1cd0d [mips] Delete all floating point instruction classes that are no longer used. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170084 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-13 02:05:02 +00:00
Akira Hatanaka
5c37399279 [mips] Modify definitions of floating point conditional move instructions. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-13 01:41:15 +00:00
Akira Hatanaka
249330eadb [mips] Shorten predicate name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169579 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-07 03:06:09 +00:00
Akira Hatanaka
ab9705f8fa [mips] Remove unnecessary predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169577 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-07 03:01:24 +00:00
Akira Hatanaka
1418045472 1. introduce MipsPat in place of Pat in order to exclude those from 
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158470 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-14 21:03:23 +00:00
Akira Hatanaka
18f3c78092 This patch adds a predicate to existing mips32 and mips64 so that those 
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157234 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-22 03:10:09 +00:00
Akira Hatanaka
2b409b65d4 Add another peephole pattern for conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156460 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 02:29:29 +00:00
Akira Hatanaka
ecdc9d5bb2 Add disassembler to MIPS. 
Patch by Vladimir Medic. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-17 18:03:21 +00:00
Akira Hatanaka
02365945a6 Revert r153924. There were buildbot failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 02:51:09 +00:00
Akira Hatanaka
885020a7a7 MIPS disassembler support. 
Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 02:20:58 +00:00
Jia Liu
bb481f8820 remove blanks, and some code format 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 07:46:26 +00:00
Jia Liu
8f5e8c1cd6 add Emacs tag and fix some comment error in file headers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 01:23:50 +00:00
Bruno Cardoso Lopes
c3f16b316a Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:50:36 +00:00
Akira Hatanaka
8ae330ac90 Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:53:29 +00:00
Akira Hatanaka
8f3af87e99 Move class and instruction definitions for conditional moves to a seperate file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 18:43:19 +00:00