6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-02 09:29:24 +00:00
Code Issues Projects Releases Wiki Activity
45,659 Commits 39 Branches 0 Tags 277 MiB
29519b1de0
Commit Graph

10362 Commits

Author SHA1 Message Date
Anton Korobeynikov
29519b1de0 Fix thinko: put stuff with both global and local relocations into data.rel{.ro}, not .local 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68036 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-30 17:37:43 +00:00
Anton Korobeynikov
fca82deecb Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68032 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-30 15:27:43 +00:00
Anton Korobeynikov
71a7c6cde0 Add data.rel stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68031 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-30 15:27:03 +00:00
Anton Korobeynikov
721c2c647e IA64 is as weird as Alpha wrt r/o relocs :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68007 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-29 17:14:35 +00:00
Anton Korobeynikov
01209bc12a Alpha always requires global relocations to be r/w regardless of PIC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68006 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-29 17:14:14 +00:00
Anton Korobeynikov
db2323148b Honour relocation behaviour stuff for ro objects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68005 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-29 17:13:49 +00:00
Chris Lattner
352f3e5d37 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67953 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-28 19:26:55 +00:00
Rafael Espindola
a0a4f07fb6 Use array_lengthof 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67950 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-28 19:02:18 +00:00
Rafael Espindola
da945e3bb2 Have only one definition of X86AddrNumOperands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67949 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-28 18:55:31 +00:00
Rafael Espindola
b449a68146 Make code a bit less brittle by no hardcoding the number 
of operands in an address in so many places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67945 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-28 17:03:24 +00:00
Evan Cheng
0b0cd9113a Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g. 
x * 40
=>
shlq    $3, %rdi
leaq    (%rdi,%rdi,4), %rax

This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq    (%rdi,%rdi,2), %rax
leaq    (%rsi,%rax,8), %rax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67917 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-28 05:57:29 +00:00
Jim Grosbach
0ede14f5c0 remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-27 23:06:27 +00:00
Rafael Espindola
705d800879 Avoid hardcoding that X86 addresses have 4 operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67848 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-27 15:57:50 +00:00
Rafael Espindola
e4d5d34cfc Use less hard coded constants to make the code less brittle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67846 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-27 15:45:05 +00:00
Rafael Espindola
a82dfca8c6 I am trying to add a segment to the X86 addresses matching to 
improve TLS support (see http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075220.html), but that code is VERY brittle.

This patch just makes it a bit more resistant.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-27 15:26:30 +00:00
Evan Cheng
9272253381 -no-implicit-float means explicit fp operations are legal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67784 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 23:06:32 +00:00
Evan Cheng
9d7b5309c2 tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67765 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 19:09:01 +00:00
Bill Wendling
a02a3dda56 Pull transform from target-dependent code into target-independent code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67742 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 06:14:09 +00:00
Chris Lattner
e7fa1f2a49 fix warning in -asserts mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67739 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 05:29:34 +00:00
Chris Lattner
e3a85838da fix some warnings in release-asserts mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67738 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 05:28:26 +00:00
Chris Lattner
d4015074e4 fix an apparently real bug exposed by a warning in -asserts mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67737 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 05:28:14 +00:00
Chris Lattner
022a27e363 fix warning in -asserts build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67736 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 05:25:59 +00:00
Bill Wendling
8b4b874cc6 Match this pattern so that we can generate simpler code: 
%a = ...
  %b = and i32 %a, 2
  %c = srl i32 %b, 1
  %d = br i32 %c, 

into

  %a = ...
  %b = and %a, 2
  %c = X86ISD::CMP %b, 0
  %d = X86ISD::BRCOND %c ...

This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67728 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 01:47:50 +00:00
Bill Wendling
bddc442a00 Doxygen-ify comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67727 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 01:46:56 +00:00
Gabor Greif
0c8f7dc67c do not rely on callee being operand 0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67681 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-25 06:32:59 +00:00
Evan Cheng
42bf74be14 CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-25 01:47:28 +00:00
Evan Cheng
7db860d4de Don't print global names twice with -asm-verbose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67667 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-25 01:08:42 +00:00
Dan Gohman
a96dc14968 I was convinced that it's ok to allow a second i8 return value 
to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67588 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 01:04:34 +00:00
Evan Cheng
f1c0ae9de5 Do not emit comments unless -asm-verbose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-24 00:17:40 +00:00
Dale Johannesen
1b25cb2416 Fix internal representation of fp80 to be the 
same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67562 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 21:16:53 +00:00
Dan Gohman
f871ccb853 Now that errs() is properly non-buffered, there's no need to 
explicitly flush it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 15:57:19 +00:00
Dan Gohman
2004eb6272 Correct some comments. Operand numbers start at 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67518 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 15:40:10 +00:00
Evan Cheng
fb11288109 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 08:01:15 +00:00
Dan Gohman
3aff0a63f9 Fix a grammaro in a comment that Bill noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67507 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 05:02:44 +00:00
Dan Gohman
82f84159e0 Add comments explaining why there's only one register for 
i8 return values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67502 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-23 04:28:24 +00:00
Bruno Cardoso Lopes
bdfbb74d34 Removed AFGR32 register class 
Handle odd registers allocation in FGR32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-21 00:05:07 +00:00
Bob Wilson
2a14c521ca Fix a few more indentation problems and an 80-column violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67416 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 23:16:43 +00:00
Bob Wilson
2dc4f54324 No functional changes. Fix indentation and whitespace only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67412 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 22:42:55 +00:00
Sanjiv Gupta
e9d81f0ad8 Fixed comment for libcalls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67373 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 14:10:20 +00:00
Sanjiv Gupta
6b830e6d0d Reformatting. Inserted code comments. Cleaned interfaces. 
Removed unncessary code. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67371 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 13:42:20 +00:00
Mon P Wang
bc65ca8de5 Added option to enable generating less precise mad (multiply addition) 
for those architectures that support the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-20 05:06:58 +00:00
Nick Lewycky
9c0f146d50 Remove strange extra semicolons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67287 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-19 05:51:39 +00:00
Nate Begeman
7cee81703d Add support to tablegen for naming the nodes themselves, not just the operands, 
in selectiondag patterns.  This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67286 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-19 05:21:56 +00:00
Bruno Cardoso Lopes
b53db4fb32 Added support for Mips O32 Calling Convention 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67280 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-19 02:12:28 +00:00
Chris Lattner
ff81ebf758 Disable the "call to immediate" optimization on x86-64. It is 
not safe in general because the immediate could be an arbitrary
value that does not fit in a 32-bit pcrel displacement.  
Conservatively fall back to loading the value into a register
and calling through it.

We still do the optzn on X86-32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67142 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-18 00:43:52 +00:00
Scott Michel
a82d3f7c57 CellSPU: 
Revert inadvertent mis-fix of fneg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67084 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-17 16:45:16 +00:00
Dan Gohman
9626447e70 Recognize bswapl as bswap too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67072 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-17 02:45:40 +00:00
Dan Gohman
d73566609e Recognize "bswapq" as an alternate spelling for the bswap instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67071 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-17 02:17:27 +00:00
Scott Michel
7ea02ffe91 CellSPU: 
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
  to the constant pool when they correspond to SPU's shufb instruction's
  special mask values. This avoids the overhead of performing a shuffle on a
  zero-filled vector just to get the special constant when the memory load
  suffices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-17 01:15:45 +00:00
Scott Michel
6e1d1470c2 CellSPU: 
Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the
llvm-gcc bootstrap a bit further along.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-16 18:47:25 +00:00