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2a6e616142
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3138 Commits

Author SHA1 Message Date
Bob Wilson
2a6e616142 Set alignment operand for NEON VST instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:42:37 +00:00
Jim Grosbach
453900814e ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:33:56 +00:00
Jim Grosbach
b327e13740 #+4 --> #4 for consistency with other asm output 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114706 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:32:38 +00:00
Jim Grosbach
45d6c1777c Fix formatting of output .s code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:03:26 +00:00
Owen Anderson
71e416ac3a Add isConditionalMove bits to X86 and ARM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 22:57:01 +00:00
Bob Wilson
40ff01a030 Set alignment operand for NEON VLD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 21:43:54 +00:00
Jim Grosbach
b2dda4bd34 never mind. I can't read, apparently 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114689 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:42:17 +00:00
Evan Cheng
676e258366 Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:42:03 +00:00
Jim Grosbach
24e6f2f802 Fix opcode value for the 'trap' instruction, keeping the type suffix on the 
constant. Hopefully the non-Darwin bots will like it...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114687 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:32:40 +00:00
Jim Grosbach
5c49b69609 explicit 'unsigned long' on constant value. Hopefully make bots happier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114686 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:08:04 +00:00
Benjamin Kramer
c8ab9eb066 Unbreak build. Jim, please review. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 18:57:26 +00:00
Jim Grosbach
2e6ae13bf6 Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't 
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 18:05:37 +00:00
Jim Grosbach
16c9a64c28 nuke unused var 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114676 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 17:58:00 +00:00
Evan Cheng
108c872466 If there are multiple unconditional branches terminating a block, eliminate all 
but the first one. Those will never be executed. There was logic to do this
but it was faulty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 06:54:40 +00:00
Jim Grosbach
637d89fe0e Add support for ELF PLT references for ARM MC asm printing. Adding a 
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 23:27:36 +00:00
Jim Grosbach
b6ec8cae3c Enable a few additional asserts in MC instruction lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 23:01:28 +00:00
Bob Wilson
b68987e4bf Change VDUPLANE DAG combiner to just return the result instead of calling 
CombineTo to avoid putting the result on the worklist.  I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 22:27:30 +00:00
Bob Wilson
0b8ccb8252 Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one 
of those.  Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 22:09:21 +00:00
Jim Grosbach
f0633e48eb add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114578 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 20:55:15 +00:00
Jim Grosbach
bfbe187593 Remove a few commented out bits 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114576 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 20:32:34 +00:00
Jim Grosbach
00d01f1a42 Add PrintSpecial() handling for in ARM MC instruction printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 18:37:14 +00:00
Jim Grosbach
a2244cb387 Add MC instruction printer support for ARM and Thumb1 jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114555 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 17:39:48 +00:00
Jim Grosbach
205a5fa8e4 Add MC instruction printer support for TB[BH] style thumb2 jump tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114553 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 17:15:35 +00:00
Jim Grosbach
1b935a3d2e Clean up comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114550 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-22 16:45:13 +00:00
Evan Cheng
691e64a54c OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 23:49:07 +00:00
Jim Grosbach
882ef2b76a Add start of support for MC instruction printer of ARM jump tables. Filling in 
the rest of it is next up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114500 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 23:28:16 +00:00
Owen Anderson
8614167572 Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes 
irrelevant, but add a new test for the new, improved functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 22:51:46 +00:00
Chris Lattner
52a261b3c1 fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 20:31:19 +00:00
Chris Lattner
fc448ff89b convert a couple more places to use the new getStore() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 18:51:21 +00:00
Bob Wilson
65ffec49f7 Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load 
and store intrinsics are represented with MemIntrinsicSDNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 17:56:22 +00:00
Jim Grosbach
532baa5d53 Fix errant printing of [v]ldm instructions that aren't a pop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114445 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 16:45:31 +00:00
Gabor Greif
8ff9bb189c Fix buglet when the TST instruction directly uses the AND result. 
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 13:30:57 +00:00
Gabor Greif
04ac81d5db Move the search for the appropriate AND instruction 
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 12:01:15 +00:00
Chris Lattner
d1c24ed81c convert the targets off the non-MachinePointerInfo of getLoad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 06:44:06 +00:00
Chris Lattner
e72f2027e9 reimplement memcpy/memmove/memset lowering to use MachinePointerInfo 
instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 05:40:29 +00:00
Chris Lattner
59db5496f4 convert targets to the new MF.getMachineMemOperand interface. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 04:39:43 +00:00
Jim Grosbach
1dc335a79f Simplify ARM callee-saved register handling by removing the distinction 
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-20 19:32:20 +00:00
Michael J. Spencer
895dda6fb5 Fix build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 17:54:37 +00:00
Eric Christopher
c109556a0a Thumb opcodes for thumb calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 02:32:38 +00:00
Eric Christopher
6dab137b88 Add addrmode5 fp load support. Swap float/thumb operand adding to handle 
thumb with floating point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 01:59:37 +00:00
Eric Christopher
b74558ad3e Floating point stores have a 3rd addressing mode type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 01:23:38 +00:00
Jim Grosbach
988ce097b7 factor out a simple helper function to create a label for PC-relative 
instructions (PICADD, PICLDR, et.al.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 00:05:05 +00:00
Jim Grosbach
d30cfde935 PC-relative pseudo instructions are lowered and printed directly. Any encounter 
with one in the generic printing code is an error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 00:04:53 +00:00
Benjamin Kramer
92aa1f7123 Fix vmov.f64 disassembly on targets where sizeof(long) != 8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 23:48:07 +00:00
Jim Grosbach
fbd1873041 Add MC-inst handling for tPICADD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 23:41:53 +00:00
Bob Wilson
75f0288b7d Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64 
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert.  Radar 8407927.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff Teach the (non-MC) instruction printer to use the cannonical names for push/pop, 
and shift instructions on ARM. Update the tests to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 22:36:38 +00:00
Eric Christopher
a5b1e68107 Rework arm fast isel branch and compare code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 22:28:18 +00:00
Jim Grosbach
74d7e6c64e Hook up verbose asm comment printing for SOImm operands in MC printer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 21:33:25 +00:00
Jim Grosbach
196b48b708 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 21:25:10 +00:00