Commit Graph

1117 Commits

Author SHA1 Message Date
Eric Christopher
9f85dccfc6 Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 21:25:23 +00:00
Matt Arsenault
fa76ba82f2 R600/SI: Fix definitions for ds_read2 / ds_write2 instructions.
These were just wrong, using the wrong register classes
and store2 was missing an operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214756 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 18:49:22 +00:00
Eric Christopher
b88bbc0e9d Move the R600 intrinsic support back to the target machine - there's
nothing subtarget dependent about the intrinsic support in any
backend as far as I can tell.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214738 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 17:37:43 +00:00
Matt Arsenault
b47e0f1d8b Use the known address space constant rather than checking it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214729 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 16:55:35 +00:00
Matt Arsenault
0ce8757b56 R600: Remove unused include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214728 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 16:55:33 +00:00
Matt Arsenault
fc65cf649c R600/SI: Fix extra whitespace in asm str
This slipped in in r214467, so something like

V_MOV_B32_e32  v0, ... is now printed with 2 spaces
between the instruction name and first operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-03 05:27:14 +00:00
Matt Arsenault
63fab54fac R600/SI: Fix formatting.
Avoid weird line wrapping of BuildMI dest register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214608 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-02 01:10:28 +00:00
Chandler Carruth
04395213ab [SDAG] MorphNodeTo recursively deletes dead operands of the old
fromulation of the node, which isn't really the desired behavior from
within the combiner or legalizer, but is necessary within ISel. I've
added a hopefully helpful comment and fixed the only two places where
this took place.

Yet another step toward the combiner and legalizer not needing to use
update listeners with virtual calls to manage the worklists behind
legalization and combining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214574 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 22:09:43 +00:00
Tom Stellard
b2df20d015 Revert "R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp"
This reverts commit r214566.

I did not mean to commit this yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214572 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 21:55:50 +00:00
Tom Stellard
7e595450fb R600/SI: Remove leftover debugging code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214569 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 21:51:05 +00:00
Tom Stellard
7f288b455e R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp
SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code
path for 8-bit and 16-bit private loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214566 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 21:50:47 +00:00
Matt Arsenault
76db85a36f R600/SI: Don't display GDS bit for read2
This isn't displayed for any other instructions anymore,
and isn't ever used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 17:00:26 +00:00
Tom Stellard
de55992d54 R600/SI: Fix build warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 02:05:57 +00:00
Tom Stellard
17c8fefc9f R600/SI: Do abs/neg folding with ComplexPatterns
Abs/neg folding has moved out of foldOperands and into the instruction
selection phase using complex patterns.  As a consequence of this
change, we now prefer to select the 64-bit encoding for most
instructions and the modifier operands have been dropped from
integer VOP3 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214467 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:39 +00:00
Tom Stellard
5494792536 R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperands
We were incorrectly assuming that all VOP2 instructions can read SGPRs
in Src0, but this is not true for instructions that read carry-in from
VCC.

The old logic has been replaced with new logic which checks the defined
register classes of the VOP2 instruction to determine whether or not to
legalize the operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214465 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:35 +00:00
Tom Stellard
635fb9fb59 R600/SI: Fold immediates when shrinking instructions
This will prevent us from using extra MOV instructions once we prefer
selecting 64-bit instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:33 +00:00
Tom Stellard
e5fc4208eb R600/SI: Fix incorrect commute operation in shrink instructions pass
We were commuting the instruction by still shrinking it using the
original opcode.

NOTE: This is a candidate for the 3.5 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:28 +00:00
Louis Gerbarg
7d54c5b0f2 Make sure no loads resulting from load->switch DAGCombine are marked invariant
Currently when DAGCombine converts loads feeding a switch into a switch of
addresses feeding a load the new load inherits the isInvariant flag of the left
side. This is incorrect since invariant loads can be reordered in cases where it
is illegal to reoarder normal loads.

This patch adds an isInvariant parameter to getExtLoad() and updates all call
sites to pass in the data if they have it or false if they don't. It also
changes the DAGCombine to use that data to make the right decision when
creating the new load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214449 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 21:45:05 +00:00
Matt Arsenault
f3e7778454 R600/SI: Remove redundant setting of bits on instructions.
neverHasSideEffects is deprecated, and hasSideEffects = 0 is already
set on the base classes of the basic ALU instruction classes. The
base classes also already set mayLoad = 0 and mayStore = 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214283 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 03:18:57 +00:00
Matt Arsenault
8ad24437bd R600/SI: Consider adjacent offsets in getLdStBaseRegImmOfs
We can treat ds_read2_* as a single offset if the offsets are adjacent.

No test since emission of read2 instructions for partially
aligned loads isn't implemented yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214269 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 01:01:10 +00:00
Matt Arsenault
37467aeaf2 R600/SI: Implement getLdStBaseRegImmOfs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214225 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 21:34:55 +00:00
Matt Arsenault
8b891ea63e R600/SI: Enable named operand table for DS instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214217 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 21:00:56 +00:00
Matt Arsenault
5479b927d6 Remove line with no effect
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214216 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 21:00:53 +00:00
Matt Arsenault
b33d6c412d R600/SI: Add isMUBUF / isMTBUF
Also add missing comments about how the flags work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 18:51:56 +00:00
Matt Arsenault
dbd003e582 R600/SI: Set bits on SMRD instructions
Set mayStore = 0 and enable named operand table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 18:51:54 +00:00
Matt Arsenault
3bd14877eb Fix typos / grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214147 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 00:02:40 +00:00
Matt Arsenault
3f8df97245 Fix header including itself
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214146 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 00:02:37 +00:00
Matt Arsenault
7505602266 R600/SI: Fix return type for isMIMG / isSMRD
All the others use bool, so these should too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214106 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-28 17:59:38 +00:00
Matt Arsenault
3a5e9cb146 R600/SI: Implement getOptimalMemOpType
The default guess uses i32. This needs an address space argument
to really do the right thing in all cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214104 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-28 17:49:26 +00:00
Matt Arsenault
e7dac08dea R600/SI: Make argument loads invariant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214101 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-28 17:31:39 +00:00
Matt Arsenault
2dd264c8a3 Add alignment value to allowsUnalignedMemoryAccess
Rename to allowsMisalignedMemoryAccess.

On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment,
and don't need to be split into multiple accesses. Vector loads with
an alignment of the element type are not uncommon in OpenCL code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214055 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-27 17:46:40 +00:00
Matt Arsenault
44c3a982c2 R600: Move intrinsic lowering to separate functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214023 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-26 06:23:37 +00:00
Matt Arsenault
ee17bf3fd4 R600/SI: Allow partial unrolling and increase thresholds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213985 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-25 23:02:42 +00:00
Eric Christopher
3aa56ba98e Move R600 subtarget dependent variables onto the subtarget.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213982 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-25 22:22:39 +00:00
Chandler Carruth
568ab6a8dc [SDAG] Enable the new assert for out-of-range result numbers in
SDValues, fixing the two bugs left in the regression suite.

The key for both of these was the use a single value type rather than
a VTList which caused an unintentionally single-result merge-value node.
Fix this by getting the appropriate VTList in place.

Doing this exposed that the comments in x86's code abouth how MUL_LOHI
operands are handle is wrong. The bug with the use of out-of-range
result numbers was hiding the bug about the order of operands here (as
best i can tell). There are more places where the code appears to get
this backwards still...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213931 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-25 09:19:23 +00:00
Matt Arsenault
855a7e6eff R600: Add FMA instructions for Evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213882 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 17:41:01 +00:00
Matt Arsenault
cb1ac70623 R600: Add new functions for splitting vector loads and stores.
These will be used in future patches and shouldn't change anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213877 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 17:10:35 +00:00
Matt Arsenault
de929f8b7d R600: Match rcp node on pre-SI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213844 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 06:59:24 +00:00
Matt Arsenault
f303d037f2 R600: Fix LowerSDIV24
Use ComputeNumSignBits instead of checking for i8 / i16 which only
worked when AMDIL was lying about having legal i8 / i16.

If an integer is known to fit in 24-bits, we can
do division faster with float ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213843 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 06:59:20 +00:00
Matt Arsenault
ba86db191d R600: Implement enableClusterLoads()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213831 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 02:10:17 +00:00
Saleem Abdulrasool
7ed655da8c R600: silence GCC warning
GCC believes it may be possible to not return a value from the switch:
  lib/Target/R600/SIRegisterInfo.cpp:187:1: warning: control reaches end of non-void function [-Wreturn-type]

Add an unreachable label to indicate that this is not possible and still permit
switch coverage checking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213572 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:52:00 +00:00
Tom Stellard
163d8ce61f R600/SI: Refactor VOP3 instruction definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213571 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:44:29 +00:00
Tom Stellard
3ee2c33655 R600/SI: Separate encoding and operand definitions into their own classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213570 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:44:28 +00:00
Tom Stellard
d7858afe79 R600/SI: Initailize encoding fields of unused VOP3 modifiers to 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213564 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:12:40 +00:00
Tom Stellard
0794af86a1 R600/SI: Initialize unused VOP3 sources to 0 instead of SIOperand.ZERO
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:12:37 +00:00
Tom Stellard
9787e8c76b R600/SI: Add instruction shrinking pass
This pass converts 64-bit instructions to 32-bit when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213561 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 16:55:33 +00:00
Tom Stellard
df99a7f5dc R600/SI: VOPC instructions explicitly define VCC
Therefore we don't need to add it to the implict defs list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 16:27:24 +00:00
Tom Stellard
05388f25d7 R600/SI: Clean up some of the unused REGISTER_{LOAD,STORE} code
There are a few more cleanups to do, but I ran into some problems
with ext loads and trunc stores, when I tried to change some of the
vector loads and stores from custom to legal, so I wasn't able to
get rid of everything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213552 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:45:06 +00:00
Tom Stellard
3280804237 R600/SI: Use scratch memory for large private arrays
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:45:01 +00:00
Tom Stellard
c912b101d2 R600/SI: Specify wavefront size for SI and CI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213550 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 15:44:58 +00:00