Commit Graph

1117 Commits

Author SHA1 Message Date
Matt Arsenault
1f4772305a R600: Use BCNT_INT for evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:28 +00:00
Matt Arsenault
69891c0115 R600/SI: Implement i64 ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:24 +00:00
Matt Arsenault
ee9772d9dd R600/SI: Use bcnt instruction for ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:18:21 +00:00
Matt Arsenault
bfd00e21b7 R600: Handle fcopysign
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 19:00:20 +00:00
Matt Arsenault
0ba78a9121 R600/SI: Handle sign_extend and zero_extend to i64 with patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:54:59 +00:00
Tom Stellard
f586a260ca SelectionDAG: Expand SELECT_CC to SELECT + SETCC
This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:01:22 +00:00
Matt Arsenault
405ed284b7 R600/SI: Rename VOP3 helper class to be more general
It has other uses besides shift instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 17:00:46 +00:00
Matt Arsenault
1968da36ed R600/SI: Keep 64-bit not on SALU
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 16:36:31 +00:00
Matt Arsenault
cf7a113d2f R600: Fix selection failure for vector bswap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 16:20:25 +00:00
Matt Arsenault
798a829eca R600/SI: Match rsq instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210226 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-05 00:15:55 +00:00
Matt Arsenault
6db82d3819 Use nullptr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210222 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-05 00:01:12 +00:00
Matt Arsenault
1b68686365 Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-03 23:06:13 +00:00
Matt Arsenault
3871a03035 R600: Set all float vector expands in the same place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-01 07:38:21 +00:00
Matt Arsenault
606b80c8c4 R600/SI: Remove redundant patterns
These patterns are already handled in the instruction definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209979 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-31 19:25:17 +00:00
Matt Arsenault
da5824d073 R600/SI: Fix [s|u]int_to_fp for i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-31 06:47:42 +00:00
Matt Arsenault
bf933548ba R600/SI: Fix pattern variable names.
These are confusing enough since the order swaps,
so give them more useful names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 01:18:01 +00:00
Matt Arsenault
fed4bab148 R600: Add definition for flat address space ID.
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:27:07 +00:00
Matt Arsenault
3c698f35e0 R600: Try to convert BFE back to standard bit ops when possible.
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209462 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:12 +00:00
Matt Arsenault
e3ed404672 R600: Add dag combine for BFE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209461 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:07 +00:00
Matt Arsenault
7e12b82625 R600: Implement ComputeNumSignBitsForTargetNode for BFE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:03 +00:00
Matt Arsenault
9859540b06 R600: Implement computeMaskedBitsForTargetNode for BFE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209459 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:09:00 +00:00
Matt Arsenault
cb0402e9a4 R600: Expand mul24 for GPUs without it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:24 +00:00
Matt Arsenault
21851f9adb R600: Expand mad24 for GPUs without it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:20 +00:00
Matt Arsenault
f49da4338a R600: Add intrinsics for mad24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 18:00:15 +00:00
Matt Arsenault
351c658fc2 R600/SI: Move instruction pattern to instruction definition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209454 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 17:45:20 +00:00
Matt Arsenault
bce7d05ba9 R600/SI: Match fp_to_uint / uint_to_fp for f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 03:20:30 +00:00
Matt Arsenault
afd1747bbc R600: Add comment describing problems with LowerConstantInitializer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209333 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:59:17 +00:00
Matt Arsenault
bd124c85ef R600: Partially fix constant initializers for structs and vectors.
This should extend the current workaround to work with structs
that only contain legal, scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209331 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:42:42 +00:00
Matt Arsenault
49323774b4 Use cast<> instead of unchecked dyn_cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209310 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 18:03:59 +00:00
Matt Arsenault
f5d9170e67 Remove unused method declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209174 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-19 22:55:35 +00:00
Aaron Ballman
50d09f1212 Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209126 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-19 14:29:04 +00:00
Tom Stellard
17200e3bb3 R600/SI: Refactor the VOP3_32 tablegen class
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:47 +00:00
Tom Stellard
9d99d7a185 R600/SI: Add a PredicateControl class for managing TableGen predicates
This was inspired by the PredicateControl class in the MIPS backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209027 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:45 +00:00
Tom Stellard
9b24e0c6f2 R600/SI: Move tablegen patterns away from instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:44 +00:00
Tom Stellard
1c073c3954 R600/SI: Remove unused instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209025 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:43 +00:00
Tom Stellard
3bd63cd655 R600/SI: Promote f32 SELECT to i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209024 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:41 +00:00
Tom Stellard
03b96200c6 R600/SI: Remove duplicate pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209023 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:56:37 +00:00
Matt Arsenault
a8f7afaeb4 Use range for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208922 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 21:44:05 +00:00
Tom Stellard
29d4ed329e R600/SI: Stop using VSrc_* as the default register class for types.
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:57 +00:00
Tom Stellard
704fe35d88 R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies
This prevents a future commit from regressing the load-i1.ll test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:55 +00:00
Tom Stellard
c1de569ce8 R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:54 +00:00
Tom Stellard
bfffad69b2 R600/SI: Use VALU instructions for i1 ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 14:41:50 +00:00
Jay Foad
6b543713a2 Rename ComputeMaskedBits to computeKnownBits. "Masked" has been
inappropriate since it lost its Mask parameter in r154011.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208811 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14 21:14:37 +00:00
Matt Arsenault
dda22295e4 R600/SI: Try to fix BFE operands when moving to VALU
This was broken by r208479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208740 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 23:45:50 +00:00
Matt Arsenault
8655b1266f Use cast<> for unchecked use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 20:42:57 +00:00
Matt Arsenault
b36e348af3 Use cast<> for unchecked use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:26:38 +00:00
Matt Arsenault
76aa42c199 Use range for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208617 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:23:21 +00:00
Matt Arsenault
5049ca67c2 R600: Add mul24 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 17:49:57 +00:00
Matt Arsenault
d0c1b54942 Fix return before else
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208510 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-11 21:24:41 +00:00
Vincent Lejeune
e283f74133 R600/SI: Fold fabs/fneg into src input modifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:39 +00:00
Vincent Lejeune
3378ca7d5c R600/SI: Prettier display of input modifiers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:33 +00:00
Vincent Lejeune
d19e830174 R600/SI: Use pseudo instruction for fabs/clamp/fneg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-10 19:18:25 +00:00
Tom Stellard
3f26d366a4 R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208432 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:42:22 +00:00
Tom Stellard
300094fd84 R600/SI: Fix SMRD pattern for offsets > 32 bits
We were dropping the high bits of 64-bit immediate offsets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208431 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:42:21 +00:00
Tom Stellard
561bb44525 R600: Expand i64 SELECT_CC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208430 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:42:19 +00:00
Tom Stellard
87b983680c R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208429 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 16:42:16 +00:00
Matt Arsenault
459ff08eaa R600: Promote f64 vector load/stores to i64 for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208344 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 18:01:56 +00:00
Tom Stellard
4b84b524e5 R600: Expand i64 ISD:SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208005 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 21:47:15 +00:00
Marek Olsak
f6518f6034 R600/SI: allow 5 more input SGPRs to a shader
Our OpenGL driver needs 22 SGPRs (16 user SGPRs + 6 streamout non-user SGPRs).

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207990 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 19:30:54 +00:00
Tom Stellard
c192d8a569 R600/SI: Add processor type for Mullins.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207846 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 15:41:49 +00:00
Tom Stellard
ab2fed6622 R600: Expand vector sin and cos.
v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207845 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 15:41:47 +00:00
Tom Stellard
1d6859256c R600: Expand TruncStore i64 -> {i16,i8}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207844 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 15:41:46 +00:00
Tom Stellard
9b22626068 R600/SI: Only create one instruction when spilling/restoring register v3
The register spiller assumes that only one new instruction is created
when spilling and restoring registers, so we need to emit pseudo
instructions for vector register spills and lower them after
register allocation.

v2:
  - Fix calculation of lane index
  - Extend VGPR liveness to end of program.

v3:
  - Use SIMM16 field of S_NOP to specify multiple NOPs.

https://bugs.freedesktop.org/show_bug.cgi?id=75005

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207843 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 15:41:42 +00:00
Matt Arsenault
2baa7c53c9 R600/SI: Fix verifier error with pseudo store instructions.
Use i32 instead of specifying SReg_32. When this is
the pseudo INDIRECT_BASE_ADDR, this would give a bogus
verifier error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207770 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 16:37:52 +00:00
Tom Stellard
bd24b33e57 R600/SI: Use VALU instructions for copying i1 values
We can't use SALU instructions for this since they ignore the EXEC mask
and are always executed.

This fixes several OpenCV tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207661 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:31:33 +00:00
Tom Stellard
1d8e31fc7a R600/SI: Teach moveToVALU how to handle some SMRD instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:31:29 +00:00
Tom Stellard
d3f1202966 R600: Remove unused function AMDGPUSubtarget::getDefaultSize()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207654 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 14:20:53 +00:00
Craig Topper
7ae9b5fc71 Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I introduced most of these recently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 07:17:30 +00:00
Craig Topper
c6b0620101 De-virtualize or remove some methods that have no overrides nor override anything. In some cases remove all together if there are no callers either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 05:53:27 +00:00
Tom Stellard
c1ff2d3621 R600: Remove duplicate setting of SELECT expansion.
It's already set in AMDGPUISelLowering for all GPUs

Patch By: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207592 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:55 +00:00
Tom Stellard
40e455d992 R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
SI_IF and SI_ELSE are terminators which also produce a value.  For
these instructions ISel always inserts a COPY to move their value
to another basic block.  This COPY ends up between SI_(IF|ELSE)
and the S_BRANCH* instruction at the end of the block.

This breaks MachineBasicBlock::getFirstTerminator() and also the
machine verifier which assumes that terminators are grouped together at
the end of blocks.

To solve this we coalesce the copy away right after ISel to make sure
there are no instructions in between terminators at the end of blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207591 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:53 +00:00
Tom Stellard
2a90e446c0 R600/SI: Only select SALU instructions in the entry or exit block
SALU instructions ignore control flow, so it is not always safe to use
them within branches.  This is a partial solution to this problem
until we can come up with something better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207590 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:48 +00:00
Tom Stellard
19a970b2da R600: optimize the UDIVREM 64 algorithm
This is a squash of several optimization commits:
 - calculate DIV_Lo and DIV_Hi separately
 - use BFE_U32 if we are operating on 32bit values
 - use precomputed constants instead of shifting in UDVIREM
 - skip the first 32 iterations of udivrem

v2: Check whether BFE is supported before using it

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207589 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:46 +00:00
Tom Stellard
ea89cd8b52 R600: Implement iterative algorithm for udivrem
Initial implementation, rather slow

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:45 +00:00
Tom Stellard
dbe7f8723a R600: Change UDIV/UREM to UDIVREM when legalizing types
When legalizing ops, with UDIV/UREM set to expand, they automatically
expand to UDIVREM (if legal or custom).
We need to do this manually for legalize types.

v2:
  SI should be set to Expand because the type is legal, and it is
    automatically lowered to UDIVREM if UDIVREM is Legal/Custom
  R600 should set to UDIV/UREM to Custom because it needs to lower them
    during type legalization

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:43 +00:00
Tom Stellard
78fc9c53e5 R600: remove unused variable
Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207586 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 23:12:38 +00:00
Craig Topper
c279ae979e [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207503 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 07:57:24 +00:00
Craig Topper
7d811a53de Convert more SelectionDAG functions to use ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207397 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 05:57:50 +00:00
Craig Topper
c34a25d59d [C++] Use 'nullptr'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207394 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 04:05:08 +00:00
Craig Topper
f564ea31f0 Convert SelectionDAG::MorphNodeTo to use ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207378 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-27 19:21:16 +00:00
Craig Topper
1aa05f3844 Convert SelectionDAG::SelectNodeTo to use ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207377 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-27 19:21:11 +00:00
Craig Topper
a7f892b33b Convert SelectionDAG::getMergeValues to use ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207374 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-27 19:20:57 +00:00
Craig Topper
72c93595de Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer and size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207329 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-26 19:29:41 +00:00
Craig Topper
80d8db7a1f Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-26 18:35:24 +00:00
Matt Arsenault
d1f361aa39 R600: Fix function name printing in LowerCall
v2: Check both ExternalSymbol and GlobalAddress

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207282 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 22:22:01 +00:00
Duncan P. N. Exon Smith
db8c1ae04e SCC: Change clients to use const, NFC
It's fishy to be changing the `std::vector<>` owned by the iterator, and
no one actual does it, so I'm going to remove the ability in a
subsequent commit.  First, update the users.

<rdar://problem/14292693>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207252 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 18:24:50 +00:00
Craig Topper
c848b1bbcf [C++] Use 'nullptr'. Target edition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 05:30:21 +00:00
Matt Arsenault
2dbbd17394 R600/SI: Use address space in allowsUnalignedMemoryAccesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207126 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 17:08:26 +00:00
Matt Arsenault
3682fdabef R600: Emit error instead of unreachable on function call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 16:42:00 +00:00
Tom Stellard
baf1d45ec2 R600/SI: Reorganize SIInstructions.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206902 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 16:33:57 +00:00
Matt Arsenault
073440f3d4 R600: Change how vector truncating stores are packed.
Don't introduce new operations on an illegal sub 32-bit type.
Do the operations on a 32-bit value, and then use a truncating store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206864 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 04:11:14 +00:00
Matt Arsenault
3ddf868b04 R600: Make sign_extend_inreg legal.
Don't know why I didn't just do this in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 03:49:30 +00:00
Chandler Carruth
42e8630239 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, lib/Target/...
edition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:41:26 +00:00
Chandler Carruth
58f58c97f0 [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some
system headers above the includes of generated '.inc' files that
actually contain code. In a few targets this was already done pretty
consistently, but it wasn't done *really* consistently anywhere. It is
strictly cleaner IMO and necessary in a bunch of places where the
DEBUG_TYPE is referenced from the generated code. Consistency with the
necessary places trumps. Hopefully the build bots are OK with the
movement of intrin.h...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206838 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:03:14 +00:00
Chandler Carruth
283b399377 [Modules] Make Support/Debug.h modular. This requires it to not change
behavior based on other files defining DEBUG_TYPE, which means it cannot
define DEBUG_TYPE at all. This is actually better IMO as it forces folks
to define relevant DEBUG_TYPEs for their files. However, it requires all
files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't
already. I've updated all such files in LLVM and will do the same for
other upstream projects.

This still leaves one important change in how LLVM uses the DEBUG_TYPE
macro going forward: we need to only define the macro *after* header
files have been #include-ed. Previously, this wasn't possible because
Debug.h required the macro to be pre-defined. This commit removes that.
By defining DEBUG_TYPE after the includes two things are fixed:

- Header files that need to provide a DEBUG_TYPE for some inline code
  can do so by defining the macro before their inline code and undef-ing
  it afterward so the macro does not escape.

- We no longer have rampant ODR violations due to including headers with
  different DEBUG_TYPE definitions. This may be mostly an academic
  violation today, but with modules these types of violations are easy
  to check for and potentially very relevant.

Where necessary to suppor headers with DEBUG_TYPE, I have moved the
definitions below the includes in this commit. I plan to move the rest
of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big
enough.

The comments in Debug.h, which were hilariously out of date already,
have been updated to reflect the recommended practice going forward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 22:55:11 +00:00
David Blaikie
52d629e1bc Use unique_ptr to manage objects owned by the ScheduleDAGMI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 20:32:32 +00:00
Benjamin Kramer
1d16fdecd6 [C++11] Replace OwningPtr with std::unique_ptr in places where it doesn't break the API.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206740 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 09:34:48 +00:00
Matt Arsenault
1b16515971 R600: Minor cleanups.
Fix indentation, better line wrapping, unused includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206562 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 07:40:20 +00:00
Matt Arsenault
746734df1a R600/SI: Try to use scalar BFE.
Use scalar BFE with constant shift and offset when possible.
This is complicated by the fact that the scalar version packs
the two operands of the vector version into one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 05:19:26 +00:00
Matt Arsenault
6834a55df3 R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206547 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 01:53:18 +00:00
Tom Stellard
cfe02c46dc R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 00:36:21 +00:00
Tom Stellard
52d940edcd R600: Add comment clariying use of sext for result of MUL_U24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206501 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 21:00:13 +00:00
Tom Stellard
93ea1378d2 R600/SI: Stop using i128 as the resource descriptor type
Having i128 as a legal type complicates the legalization phase.  v4i32
is already a legal type, so we will use that instead.

This fixes several piglit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 21:00:11 +00:00
Tom Stellard
ec6e62ec98 R600/SI: Change default register class for i32 to SReg_32
SIFixSGPRCopies is smart enough to handle this now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206499 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 21:00:09 +00:00
Tom Stellard
c2bab04829 R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206498 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 21:00:07 +00:00
Tom Stellard
1b011b51ea R600/SI: Legalize operands after changing dst reg in FixSGPRCopies
Otherwise we may not legalize some illegal REG_SEQUENCE instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206497 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 21:00:01 +00:00
Matt Arsenault
9e383d4b48 R600/SI: f64 frint is legal on CI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 17:06:37 +00:00
Matt Arsenault
003de065a3 R600/SI: Fix zext from i1 to i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-17 02:03:08 +00:00
Craig Topper
5422dfb5b0 Convert SelectionDAG::getVTList to use ArrayRef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206357 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 06:10:51 +00:00
Matt Arsenault
ff8d7fb136 R600: Expand sign extension of vectors.
Setting vector types to expand will result in scalarization on pre SI hw,
as those gpus don't have vector shifts either.
Expand also i32 vectors, this helps llvm make the correct decision
about scalarizing the vector ops.

v2: move setOperation() calls to R600ISelLowering.cpp.
    cleanup the SI code to make it obvious that this patch does is nop for SI

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 01:41:30 +00:00
Matt Arsenault
d66d570796 R600/SI: Print code size along with used registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:40:47 +00:00
Matt Arsenault
bec5c611e1 R600/SI: Print more immediates in hex format
Print in decimal for inline immediates, and hex otherwise. Use hex
always for offsets in addressing offsets.

This approximately matches what the shader compiler does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206335 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:32:49 +00:00
Matt Arsenault
dd368a8755 R600/SI: Cleanup parsing of register names.
Try to figure out the class and number of subregisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:32:42 +00:00
Matt Arsenault
f8ea0352e0 R600/SI: Fix loads of i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206330 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:28:39 +00:00
Nick Lewycky
d63390cba1 Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206255 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 07:22:52 +00:00
Matt Arsenault
4aee5942c3 R600: Check if a sextload should be used for parameter loads.
Through some oddity where truncate (sextload x) isn't folded into
an anyextload for vectors, the sextload remains if the
vector isn't immediately scalarized. This keeps the expected
zextload instructions in the kernel-args test when small type
vectors aren't scalarized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206070 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-11 20:59:54 +00:00
Matt Arsenault
6e6126ac4c R600/SI: Refactor SOPC classes slightly.
Better match what is done for VOPC to eventually
prefer selecting these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206048 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-11 19:25:18 +00:00
Matt Arsenault
d879166376 Move ExtractVectorElements to SelectionDAG.
This seems generally useful, and makes sense to
go along with SplitVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206041 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-11 17:47:30 +00:00
David Blaikie
77cf856e56 Implement depth_first and inverse_depth_first range factory functions.
Also updated as many loops as I could find using df_begin/idf_begin -
strangely I found no uses of idf_begin. Is that just used out of tree?

Also a few places couldn't use df_begin because either they used the
member functions of the depth first iterators or had specific ordering
constraints (I added a comment in the latter case).

Based on a patch by Jim Grosbach. (Jim - you just had iterator_range<T>
where you needed iterator_range<idf_iterator<T>>)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206016 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-11 01:50:01 +00:00
NAKAMURA Takumi
accaa640cf LLVMBuild.txt: Add missing dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205962 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 11:16:47 +00:00
NAKAMURA Takumi
6c5bb2e764 LLVMBuild.txt: Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205961 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 11:16:17 +00:00
Matt Arsenault
d4786ed1de R600/SI: Match not instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 07:16:16 +00:00
Tom Stellard
1d8c7eb225 R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:45:45 +00:00
Tom Stellard
5c9bb7119a R600: Match 24-bit arithmetic patterns in a Target DAGCombine
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:45:41 +00:00
Tom Stellard
dd2d430352 R600: Replace dyn_cast + assert with cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205730 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:31:13 +00:00
Matt Arsenault
939ec8514d Use std::swap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205723 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 16:44:26 +00:00
Matt Arsenault
e3e086ea00 Use .data() instead of &x[0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 16:44:24 +00:00
David Blaikie
b29a2b0c4c MachineInstr: introduce explicit_operands and implicit_operands ranges
Makes iteration over implicit and explicit machine operands more
explicit (har har). Insipired by code review discussion for r205565.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205680 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-05 22:42:04 +00:00
Matt Arsenault
912154008a Fix tabs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205648 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 20:13:08 +00:00
Craig Topper
84f7f350c3 Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 05:16:06 +00:00
Tom Stellard
a7469745de R600: Correct opcode for BFE_INT
Acording to AMD documentation, the correct opcode for
BFE_INT is 0x5, not 0x4

Fixes Arithm/Absdiff.Mat/3 OpenCV test

Patch by: Bruno Jiménez

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205562 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:19:29 +00:00
Tom Stellard
50c16fb65c R600/SI: Lower 64-bit immediates using REG_SEQUENCE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205561 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 20:19:27 +00:00
Matt Arsenault
c779918bcd R600/SI: Remove leftover pattern splitting 64-bit ors.
It's now matched to the scalar 64-bit or and split later if
necessary.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205252 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 21:46:46 +00:00
Matt Arsenault
8d8c507bbf Change shouldSplitVectorElementType to better match the description.
Pass the entire vector type, and not just the element.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205247 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 20:54:58 +00:00
Matt Arsenault
4065ed4eb0 R600/SI: Implement shouldConvertConstantLoadToIntImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205244 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 19:54:27 +00:00
Matt Arsenault
193c3e91b9 R600: Compute masked bits for min and max
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205242 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 19:35:33 +00:00
Matt Arsenault
828bfc7350 R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205236 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 18:21:18 +00:00
Matt Arsenault
894fa802f5 R600: Add target nodes for BFM and BFI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205235 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 18:21:13 +00:00
Tom Stellard
aa23732edd R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205188 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:01:56 +00:00
Tom Stellard
1f143aa3e9 R600/SI: Lower i64 SELECT by bitcasting to a vector type
This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered
using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:01:55 +00:00
Tom Stellard
1eaaa949f6 R600/SI: Return the correct index for VGPRs in getHWRegIndex()
The register index is stored in the low 8-bits of the encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:01:52 +00:00
Rafael Espindola
224dbf4aec Completely rewrite ELFObjectWriter::RecordRelocation.
I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it had:

* It failed to check if a symbol difference was in the some section when
  converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
  relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
  requiring a quiet nasty work around in ARM.
* It was missing comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 06:26:49 +00:00
Tim Northover
bd2cca79b7 R600: avoid calling std::next on an iterator that might be end()
This was causing my llc to go into an infinite loop on
CodeGen/R600/address-space.ll (just triggered recently by some allocator
changes).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205005 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 13:52:56 +00:00
Rafael Espindola
74dcb03fa9 Remove another unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204961 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 20:49:35 +00:00
Rafael Espindola
0c0cd3a4ee Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204956 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 20:41:17 +00:00
Matt Arsenault
0c6d96cf16 R600: Implement isZExtFree.
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 17:23:31 +00:00
Matt Arsenault
94687c0f43 R600/SI: Fix unreachable with a sext_in_reg to an illegal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204945 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 17:23:24 +00:00
Matt Arsenault
e0e503801f R600: Add a testcase for sext_in_reg I missed.
This sext_inreg i32 in i64 case was already handled, but not enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204840 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 18:31:06 +00:00
Matt Arsenault
ab5382f5eb R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp
Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-25 18:18:27 +00:00
Matt Arsenault
e130844e41 R600: Don't viewCFG() under DEBUG() except on failure.
Having these popping up every time you use -debug is really
irritating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:29:02 +00:00
Matt Arsenault
add2e2ec8f R600/SI: Fix extra mov from legalizing 64-bit SALU ops.
Check the register class of each operand individually
to avoid an extra copy to a vgpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:08:13 +00:00
Matt Arsenault
3a96e61469 R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.
No longer asserts, but now you get moves loading legal immediates
into the split 32-bit operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204661 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:08:09 +00:00
Matt Arsenault
db1807144a R600/SI: Fix 64-bit bit ops that require the VALU.
Try to match scalar and first like the other instructions.
Expand 64-bit ands to a pair of 32-bit ands since that is not
available on the VALU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 20:08:05 +00:00
Matt Arsenault
6c199d8212 R600: Implement isNarrowingProfitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 19:43:31 +00:00
Matt Arsenault
03cd663eb1 R600/SI: Move splitting 64-bit immediates to separate function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204651 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 18:26:52 +00:00
Matt Arsenault
875870fdb4 R600/SI: Fix 64-bit private loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204630 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 17:50:46 +00:00
Tom Stellard
4ddee6a5da R600/SI: Fix warning with gcc 4.8.2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:12:34 +00:00
Tom Stellard
65b5e9b4ef R600/SI: Promote fp64 SELECT to i64
This type promotion is replacing a Tablegen pattern and it is already
covered by existing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204617 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:07:30 +00:00
Tom Stellard
9958475129 R600: Reorganize tablegen instruction definitions
Each GPU family now has its own file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 16:07:25 +00:00
Matt Arsenault
55d17f4842 R600/SI: Move instruction patterns to scalar versions.
Some of them also had the pattern on both, so this removes the
duplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204492 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 18:01:18 +00:00
Tom Stellard
a1d28f6dd7 R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 15:51:57 +00:00
Tom Stellard
1f1c0495d0 R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 15:51:54 +00:00
Tom Stellard
af4c7da306 R600/SI: Use SGPR_(32|64) reg clases when lowering SI_ADDR64_RSRC
The SReg_(32|64) register classes contain special registers in addition
to the numbered SGPRs.  This can lead to machine verifier errors when
these register classes are used as sub-registers for SReg_128, since
SReg_128 only uses the numbered SGPRs.

Replacing SReg_(32|64) with SGPR_(32|64) fixes this problem, since
the SGPR_(32|64) register classes contain only numbered SGPRs.

Tests cases for this are comming in a later commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204474 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 15:51:53 +00:00
Matt Arsenault
31bd14fc2d R600: Remove unused method declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204357 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 16:41:06 +00:00
Matt Arsenault
925147ca20 R600/SI: Add unused LDS 2 form instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204275 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 22:19:56 +00:00
Matt Arsenault
e3620da269 R600/SI: Add support for 64-bit LDS writes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204274 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 22:19:54 +00:00
Matt Arsenault
62b3e22092 R600/SI: Add support for 64-bit LDS loads.
v2:
  -Use correct opcode for DS_READ_64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204273 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 22:19:52 +00:00
Matt Arsenault
6eaa49233f R600/SI: Match i16 immediate offset of LDS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204272 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 22:19:49 +00:00
Matt Arsenault
9c0b2d08d3 R600/SI: Don't display the GDS bit.
It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204270 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 22:19:43 +00:00
Matt Arsenault
6d1781733d R600/SI: Merge offset0 and offset1 fields for single address DS instructions v2
Also remove unused data fields from the DS_Load_Helper class.

v2:
  - Merge fields for DS_WRITE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204269 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 22:19:39 +00:00
Matt Arsenault
9f44c113bd Make methods static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 22:23:09 +00:00
Matt Arsenault
2683baa8ac R600: Match sign_extend_inreg to BFE instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204072 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 18:58:11 +00:00
Tom Stellard
ad52f4f70c R600/SI: Fix implementation of isInlineConstant() used by the verifier
The type of the immediates should not matter as long as the encoding is
equivalent to the encoding of one of the legal inline constants.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204056 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 17:03:52 +00:00
Tom Stellard
eb7876083d R600/SI: Use correct dest register class for V_READFIRSTLANE_B32
This instructions writes to an 32-bit SGPR.  This change required adding
the 32-bit VCC_LO and VCC_HI registers, because the full VCC register
is 64 bits.

This fixes verifier errors on several of the indirect addressing piglit
tests.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204055 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 17:03:51 +00:00
Tom Stellard
27b614fcd3 R600/SI: Add generic checks to SIInstrInfo::verifyInstruction()
Added checks for number of operands and operand register classes.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204054 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 17:03:49 +00:00
Matt Arsenault
2345166d2f R600: Remove unnecessary attempt to zext a pointer.
Private pointers are now always 32-bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203989 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-15 00:08:26 +00:00
Matt Arsenault
2cf43de915 R600: Code cleanup.
Use sign_extend_inreg and getZeroExtendInReg instead of
using the bit operations they expand into.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-15 00:08:22 +00:00
Owen Anderson
bf63022492 Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&.  At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 23:12:04 +00:00
Tom Stellard
47feea0802 R600: LDS instructions shouldn't implicitly define OQAP
LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.

This fixes a hang in the opencv MedianFilter tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203818 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 17:13:04 +00:00
Matt Arsenault
054f4eccd2 R600: Fix trunc store from i64 to i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203695 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 18:45:52 +00:00
Matt Arsenault
0e5b4860b5 R600: Calculate store mask instead of using switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 01:38:53 +00:00
Matt Arsenault
bea18e3849 Remove incomplete comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203518 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:01:37 +00:00
Matt Arsenault
6cf9da3d85 Move trivial getter into header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203517 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:01:34 +00:00
Matt Arsenault
cc1240ee1b Use .data() instead of &x[0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203516 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:01:31 +00:00
Matt Arsenault
60616b61dc Fix indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 00:01:27 +00:00
Chandler Carruth
436906ab3c [TTI] There is actually no realistic way to pop TTI implementations off
the stack of the analysis group because they are all immutable passes.
This is made clear by Craig's recent work to use override
systematically -- we weren't overriding anything for 'finalizePass'
because there is no such thing.

This is kind of a lame restriction on the API -- we can no longer push
and pop things, we just set up the stack and run. However, I'm not
invested in building some better solution on top of the existing
(terrifying) immutable pass and legacy pass manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-10 02:45:14 +00:00
Tom Stellard
6cadd406cc R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 20:12:39 +00:00
Tom Stellard
7e06370873 R600/SI: Custom lower i1 stores
These are sometimes created by the shrink to boolean optimization in the
globalopt pass.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203280 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 20:12:33 +00:00
Matt Arsenault
161e3a80b2 R600: Fix extloads from i8 / i16 to i64.
This appears to only be working for global loads. Private
and local break for other reasons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:34:12 +00:00
Matt Arsenault
b4cd160bb9 R600/SI: Expand selects on vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203134 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:34:03 +00:00
Matt Arsenault
0c5c3b93d8 Fix missing C++ mode comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203133 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:33:58 +00:00
Chandler Carruth
67f6bf70d2 [Layering] Move InstVisitor.h into the IR library as it is pretty
obviously coupled to the IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203064 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 03:23:41 +00:00
Matt Arsenault
af0cc459bf Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203013 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 21:47:22 +00:00
Chandler Carruth
7225e27b4c [Modules] Move ValueMap to the IR library. While this class does not
directly care about the Value class (it is templated so that the key can
be any arbitrary Value subclass), it is in fact concretely tied to the
Value class through the ValueHandle's CallbackVH interface which relies
on the key type being some Value subclass to establish the value handle
chain.

Ironically, the unittest is already in the right library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202824 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 11:26:31 +00:00
Benjamin Kramer
d628f19f5d [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
Remove the old functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 12:27:27 +00:00
Craig Topper
629b96cb4f Switch all uses of LLVM_OVERRIDE to just use 'override' directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 09:09:27 +00:00
Craig Topper
4eb03f049e Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 08:08:51 +00:00
Tom Stellard
34faf78241 R600: Verify all instructions in the AsmPrinter on debug builds
Make a call to R600's implementation of verifyInstruction() to
check that instructions are only using legal operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 21:36:41 +00:00
Tom Stellard
9f0d68f522 R600/SI: Expand all v16[if]32 operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 21:36:37 +00:00
Rafael Espindola
b9e06b97ce Remove MCPureStreamer.
We moved MCJIT to use native object formats a long time ago and R600
now uses ELF, so it was dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 16:17:34 +00:00
Michel Danzer
644aecfc97 R600/SI: Optimize SI_KILL for constant operands
If the SI_KILL operand is constant, we can either clear the exec mask if
the operand is negative, or do nothing otherwise.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 01:47:09 +00:00
Michel Danzer
a5fbf24716 R600/SI: Allow SI_KILL for geometry shaders
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 01:47:02 +00:00
Matt Arsenault
3f19b69b01 R600: Remove unnecessary build_vector pattern.
It is already fully handled in AMDGPUISelDAGToDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202312 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 23:00:58 +00:00
Tom Stellard
431e9f0310 R600: Don't unconditionally unroll loops with private memory accesses
This causes the size of the scrypt kernel to explode and eats all the
memory on some systems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:21 +00:00
Tom Stellard
d8c31046a9 R600/SI: Custom select 64-bit ADD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:18 +00:00
Matt Arsenault
2e4ab2aa8a Fix unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:16:50 +00:00
Matt Arsenault
bc247e4afd R600/SI - Add new CI arithmetic instructions.
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202077 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:28 +00:00
Matt Arsenault
3f9f4bc0af R600: Make check clearer.
The check is clearer as southern islands or later,
rather than checking for later than northern islands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:23 +00:00
Matt Arsenault
e87a1a9e2c Fix DOT4 missing from getTargetOpcodeName
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202075 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:21 +00:00
Tom Stellard
0f2e653317 R600/SI: Expand all v8[if]32 operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201371 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:15 +00:00
Tom Stellard
9757ba1206 R600/SI: Add a pattern for i32 anyext
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201370 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:13 +00:00
Tom Stellard
130f271259 R600/SI: Completely Disable TypeRewriter on compute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201369 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:12 +00:00
Tom Stellard
1a52c2b25a R600/SI: Split global vector loads with more than 4 elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201368 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:10 +00:00
Benjamin Kramer
eee40f92a9 R600: Always implement both versions of isTruncateFree and add a sanity check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201222 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-12 10:17:54 +00:00
Matt Arsenault
69bc4ddf10 R600/SI: Fix assertion on infinite loops.
This isn't the most useful case to fix in the real world,
but bugpoint runs into this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201177 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 21:12:38 +00:00
Matt Arsenault
700bba297b R600: Implement isTruncateFree
Truncation is just accessing a subregister for any multiple of
the register size, so it's free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 19:57:42 +00:00
Tom Stellard
42faffddb9 R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used
DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0.  When M0 is uninitialized,
then we experience undefined behavior.

This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201097 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 16:58:30 +00:00
Tom Stellard
835f1c01bf R600/SI: Only use S_WQM_B64 in pixel shaders
This doesn't change any functionality, since we only have two shader
types (compute and pixel) that use local memory.  We're just changing
the logic to match the documentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201096 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 16:58:27 +00:00
Tom Stellard
226bd876c6 R600/SI: Add a MUBUF store pattern for Reg+Imm offsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200935 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:41 +00:00
Tom Stellard
603cd56372 R600/SI: Add a MUBUF store pattern for Imm offsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200934 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:39 +00:00
Tom Stellard
becac0f183 R600/SI: Add a MUBUF load pattern for Reg+Imm offsets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200933 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:38 +00:00
Tom Stellard
22274378d5 R600/SI: Use immediates offsets for SMRD instructions whenever possible
There was a problem with the old pattern, so we were copying some
larger immediates into registers when we could have been encoding
them in the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:34 +00:00
Matt Arsenault
bb7bf85f3c Add address space argument to allowsUnalignedMemoryAccess.
On R600, some address spaces have more strict alignment
requirements than others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 23:15:53 +00:00
Michel Danzer
cf4061a601 R600/SI: Add pattern for zero-extending i1 to i32
Fixes opencl-example if_* tests with radeonsi.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200830 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 09:48:05 +00:00
Duncan P. N. Exon Smith
483727da48 cleanup: scc_iterator consumers should use isAtEnd
No functional change.  Updated loops from:

    for (I = scc_begin(), E = scc_end(); I != E; ++I)

to:

    for (I = scc_begin(); !I.isAtEnd(); ++I)

for teh win.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200789 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 19:19:07 +00:00
Rafael Espindola
5e47632b8f Every target uses .align. Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200782 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 18:39:51 +00:00
Tom Stellard
7d9ed1cac5 R600/SI: Expand i1 BR_CC
This fixes a crashes in the OpenCV test suite and also the scrypt
kernel in bfgminer.

I was unable to come up with a reduced test case for this.

https://bugs.freedesktop.org/show_bug.cgi?id=72785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200776 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:18:43 +00:00
Tom Stellard
0c7a6b6477 R600/SI: Don't assume copies will be coalesced in SIFixSGPRCopies
There is no lit test for this, because it would be too big and
complicated, but it does fix a crash in the Arithm/Absdiff.* OpenCV test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200775 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:18:42 +00:00
Tom Stellard
83918a2ad2 R600/SI: Custom lower i64 ISD::SELECT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:18:40 +00:00
Tom Stellard
4ee42eaec9 R600: Enable vector fpow.
The OpenCL specs say: "The vector versions of the math functions operate
component-wise. The description is per-component."

Patch by: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200773 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:18:37 +00:00
Michel Danzer
de2e0bc366 R600/SI: Fix fneg for 0.0
V_ADD_F32 with source modifier does not produce -0.0 for this. Just
manipulate the sign bit directly instead.

Also add a pattern for (fneg (fabs ...)).

Fixes a bunch of bit encoding piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 07:12:38 +00:00
Matt Arsenault
2a3e343d86 Add DEBUG_TYPE to SIAnnotateControlFlow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200720 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-03 22:58:05 +00:00
Matt Arsenault
b2abb9752e R600/SI: Fix insertelement with dynamic indices.
This didn't work for any integer vectors, and didn't
work with some sizes of float vectors. This should now
work with all sizes of float and i32 vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200619 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-02 00:05:35 +00:00
Rafael Espindola
9d96045528 Remove the last hasRawTextSupport call from R600.
There is nothing wrong with printing the disassembly section when printing
text. An hypothetical assembler would then produce a .o just like our
direct object emission produces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 22:14:06 +00:00
Rafael Espindola
b8f1606076 Replace another use with hasRawTextSupport+EmitRawText with emitRawComment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 22:08:19 +00:00
Rafael Espindola
f7af9eac1b Use emitRawComment to avoid a call to hasRawTextSupport.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 21:54:49 +00:00
David Woodhouse
eab5cc34c6 Delete MCSubtargetInfo data members from target MCCodeEmitter classes
The subtarget info is explicitly passed to the EncodeInstruction
method and we should use that subtarget info to influence any
encoding decisions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200350 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 23:13:25 +00:00
David Woodhouse
4faa861f19 Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200349 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 23:13:18 +00:00
David Woodhouse
2ddea4b44d Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 23:13:07 +00:00
David Woodhouse
4396f5d9d2 Change MCStreamer EmitInstruction interface to take subtarget info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200345 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 23:12:42 +00:00
Michel Danzer
f555fb410e R600/SI: Add pattern for truncating i32 to i1
Fixes half a dozen piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200283 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 03:01:16 +00:00
Michel Danzer
7018cd5af7 R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200196 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 07:20:51 +00:00
Michel Danzer
b3bfe7f18c R600/SI: Add intrinsic for S_SENDMSG instruction
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 07:20:44 +00:00
Rafael Espindola
888177e91b Add back spaces I missed in the conversion to emitRawComments.
Sorry about that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 00:19:41 +00:00
Rafael Espindola
e881f38db6 Use emitRawComment instead of EmitRawText.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200170 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 00:16:00 +00:00
Rafael Espindola
550d791907 Pass a MCSubtargetInfo down to the TargetStreamer creation.
With this the target streamers will be able to know the target features that
are in use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 06:38:58 +00:00
Rafael Espindola
aa75693ea4 Construct the MCStreamer before constructing the MCTargetStreamer.
This has a few advantages:
* Only targets that use a MCTargetStreamer have to worry about it.
* There is never a MCTargetStreamer without a MCStreamer, so we can use a
  reference.
* A MCTargetStreamer can talk to the MCStreamer in its constructor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200129 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 06:06:37 +00:00
Juergen Ributzka
8346f147ab Add final and owerride keywords to TargetTransformInfo's subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200021 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 18:22:59 +00:00
Alp Toker
ae43cab6ba Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 17:20:08 +00:00
Tom Stellard
63875e620f R600: Remove successive JUMP in AnalyzeBranch when AllowModify is true
This fixes a crash in the OpenCV OpenCL test suite.

There is no lit test for this, because the test would be very large
and could easily be invalidated by changes to the scheduler
or other parts of the compiler.

Patch by:  Vincent Lejeune

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199919 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 18:49:34 +00:00