2adc05cf5b
Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25819 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 22:20:49 +00:00
02568ff48d
i64 -> f32, f32 -> i64 and some clean up.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25818 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 22:13:22 +00:00
6dab05363f
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
...
conversions. SSE does not have instructions to handle these tasks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25817 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 08:02:57 +00:00
3772bcb333
Revamp the ICC/FCC reading instructions to be parameterized in terms of the
...
SPARC condition codes, not in terms of the DAG condcodes. This allows us to
write nice clean patterns for cmovs/branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25815 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 07:43:04 +00:00
9072c05cd8
Compile:
...
uint %test(uint %X) {
%Y = call uint %llvm.ctpop.i32(uint %X)
ret uint %Y
}
to:
test:
save -96, %o6, %o6
sll %i0, 0, %l0
popc %l0, %i0
restore %g0, %g0, %g0
retl
nop
instead of to 40 logical ops. Note the shift-by-zero that clears the top
part of the 64-bit V9 register.
Testcase here: CodeGen/SparcV8/ctpop.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25814 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 06:14:02 +00:00
5295de7c41
If the target has V9 instructions, this pass is a noop, don't bother
...
running it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25811 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:51:14 +00:00
b34d3fd4cf
When in v9 mode, emit fabsd/fnegd/fmovd
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25810 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:48:37 +00:00
76afdc9a80
First step towards V9 instructions in the V8 backend, two conditional move
...
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
6f63001214
Two changes:
...
1. Default to having V9 instructions, instead of just V8.
2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25807 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 04:57:43 +00:00
dea9528f7f
When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold
...
the two operations together. This allows us to compile this:
void %two(int %a, int* %b) {
%tmp.2 = seteq int %a, 0
%tmp.0.0 = select bool %tmp.2, int 10, int 20
store int %tmp.0.0, int* %b
ret void
}
into:
two:
save -96, %o6, %o6
or %g0, 20, %l0
or %g0, 10, %l1
subcc %i0, 0, %l2
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
st %l1, [%i1]
restore %g0, %g0, %g0
retl
nop
instead of:
two:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
or %g0, 20, %l2
or %g0, 10, %l3
subcc %i0, 0, %l4
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
subcc %l1, 0, %l0
bne .LBBtwo_4 ! entry
nop
.LBBtwo_3: ! entry
or %g0, %l2, %l3
.LBBtwo_4: ! entry
st %l3, [%i1]
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25806 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 04:34:44 +00:00
c6fd6cd65c
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25803 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 04:09:27 +00:00
4a397e0e94
Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,
...
allowing redundant and's to be eliminated by the dag combiner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25800 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 03:51:45 +00:00
87c890a9c2
adjust prototype
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25798 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 03:49:07 +00:00
37dd6f1b79
Functions that are lazily streamed in from the .bc file are *not* external.
...
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25793 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 20:49:17 +00:00
c7097afe51
add another note
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25789 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 09:46:06 +00:00
5164a313e0
add some performance notes from looking at sgefa
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25788 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 09:42:20 +00:00
6a28456e18
add a high-priority SSE issue from sgefa
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25787 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 09:14:47 +00:00
b638cd89db
add a missed optimization
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25786 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 09:08:15 +00:00
d9b55dd21a
Now that OpActions is big enough, we can specify actions for vector types
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25784 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 08:41:37 +00:00
3fd327fe7f
disable this for now
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25778 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 07:31:33 +00:00
2ce5b263ba
Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a
...
few stores under certain conditions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25777 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:48:25 +00:00
0fc9c26e7d
remove now-dead code, the legalizer takes care of this for us
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25776 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:45:31 +00:00
44d9b9bb86
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
...
instead of lying and saying we have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25775 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:44:22 +00:00
ec4a0c7c6b
Request expansion of ConstantVec nodes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25773 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:32:58 +00:00
a54aa94197
Targets all now request ConstantFP to be legalized into TargetConstantFP.
...
'fpimm' in .td files is now TargetConstantFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25771 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:26:08 +00:00
08a90229ae
Update alpha to reflect recent constantfp legalize changes. It's not clear
...
why all this code isn't autogenerated. :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25770 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 06:25:22 +00:00
c7e1852d63
cmovle != cmovlt
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25761 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 03:47:30 +00:00
b8643ac476
Fix typo.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25760 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-29 03:45:35 +00:00
c4013d6772
Flesh out AMD family/models.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25755 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 20:30:18 +00:00
216d281d0a
Correctly determine CPU vendor.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25754 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 19:48:34 +00:00
a349640b7f
Use union instead of reinterpret_cast.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25751 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 18:47:32 +00:00
7617717496
Fix recognition of Intel CPUs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25750 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 18:38:20 +00:00
c2fad16155
Is64Bit reflects the capability of the chip, not an aspect of the target os
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25749 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 18:23:48 +00:00
dabbc98396
Fix a bunch of JIT failures with the new isel
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25748 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 18:19:37 +00:00
41adb0d679
Improve X86 subtarget support for Windows and AMD.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25747 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 18:09:06 +00:00
6b2469c1ad
silence a warning
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25745 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 10:34:47 +00:00
e00ebf0aca
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
...
provide the expansion for i64 calls itself
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25735 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 07:33:03 +00:00
1e39a15b42
make this work on non-native hosts
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25734 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 06:05:41 +00:00
969097968c
add a note about how we should implement this FIXME from the legalizer:
...
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25733 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 05:40:47 +00:00
0aed7840ec
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25726 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 03:14:31 +00:00
eb20ed6c86
Add a couple more things to the readme.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25724 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 01:22:10 +00:00
34fa038f0c
Remove some dead code
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25719 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 00:02:51 +00:00
2d90bd5f42
Switch to AlphaISD::CALL instead of ISD::CALL
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25718 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 23:39:00 +00:00
281b55ebec
Use PPCISD::CALL instead of ISD::CALL
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25717 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 23:34:02 +00:00
44ea7b1a6c
Use V8ISD::CALL instead of ISD::CALL
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25716 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 23:30:03 +00:00
d41e9e5e7a
A bit of wisdom from Chris on the last entry.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25715 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 22:54:32 +00:00
85214ba3cc
AT&T assembly convention: registers are in lower case.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25714 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 22:53:29 +00:00
184cc4ac60
initialize member vars
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25712 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 22:38:36 +00:00
104988a16a
initialize all instance vars
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 22:37:09 +00:00
bba534dc66
Make llvm.frame/returnaddr not crash on ppc
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25710 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 22:25:06 +00:00