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2e35047947
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14585 Commits

Author SHA1 Message Date
Devang Patel
2e35047947 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 18:09:58 +00:00
Nadav Rotem
6fe4e51547 Add support for legalization of vector SHL/SRA/SRL instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 14:36:35 +00:00
Nick Lewycky
b1b8f5f7cd Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take 
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:58:11 +00:00
Craig Topper
a6f386b4cd Test case for X86 LZCNT instruction selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141652 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:47:01 +00:00
Craig Topper
37f2167f15 Add X86 LZCNT instruction. Including instruction selection support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:44:02 +00:00
Cameron Zwarich
66b20c4db6 Add a test for PR10565. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:10:37 +00:00
Cameron Zwarich
446d95224b Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's 
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141646 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:10:30 +00:00
Bill Wendling
3606f75f35 Test simplification that Ana Pazos noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 04:43:15 +00:00
Craig Topper
29480fd798 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 04:34:23 +00:00
Nick Lewycky
7aabcb1fc0 Also create a shndx even if there are no symbols. This lets us test 
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 03:54:50 +00:00
NAKAMURA Takumi
b1044b042f test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 03:41:03 +00:00
Andrew Trick
204494149b Move replaceCongruentIVs into SCEVExapander and bias toward "expanded" 
IVs.

Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 02:28:51 +00:00
Akira Hatanaka
b58078be33 Test cases for 64-bit load and store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141631 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 01:52:31 +00:00
Lang Hames
eafc8192d1 Added a testcase for r141599, rdar://problem/10063881. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141628 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 01:32:10 +00:00
Bill Wendling
26e8ca34fe Add testcase for PR11107. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:26:57 +00:00
Devang Patel
db7334dbc5 Revert r141569 and r141576. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 23:18:02 +00:00
Bill Wendling
ef2c86f876 Reapply r141365 now that PR11107 is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:59:55 +00:00
Eli Friedman
dca62d53b7 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:28:47 +00:00
Nick Lewycky
023bb15bea Add support for dumping section headers to llvm-objdump. This uses the same 
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 21:21:34 +00:00
Devang Patel
6b50bc9d88 If loop header is also loop exiting block then it may not be safe to hoist instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 20:32:03 +00:00
Nadav Rotem
a7934dd8e4 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:31:45 +00:00
Devang Patel
9ac743a4ee Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:09:20 +00:00
Benjamin Kramer
a86a58695d X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:34:56 +00:00
Jakob Stoklund Olesen
a0ed0c0fcd Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:30:16 +00:00
Bill Wendling
eba564ceac Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:27:30 +00:00
Benjamin Kramer
5d53ff54c0 XFAIL tblgen tests on leak checkers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141533 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 13:09:59 +00:00
Bill Wendling
8129d21396 When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 07:24:23 +00:00
Craig Topper
da394041c4 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
ed74482704 Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen
a55f6575ae Add missing test case for r141410. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141498 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 18:06:54 +00:00
Andrew Trick
861a410cb6 Unit test for LSR phi reuse in r141442. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 02:34:51 +00:00
Michael J. Spencer
27781b78e1 llvm-objdump: Add relocation and archive support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 00:18:30 +00:00
Jim Grosbach
051fee0312 Enable ARM mode VDUP(scalar) tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141447 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:57:03 +00:00
Jim Grosbach
460a90540b ARM NEON assembly parsing and encoding for VDUP(scalar). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:56:00 +00:00
David Greene
a1b1b79be1 Remove Multidefs 
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 18:25:05 +00:00
Evan Cheng
7c1780c5fe High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 17:21:44 +00:00
Bob Wilson
6d2f9cec71 Reenable tail calls for iOS 5.0 and later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 17:17:49 +00:00
Bob Wilson
2fef4573df Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:59:21 +00:00
Anton Korobeynikov
244455e6d6 Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:15:08 +00:00
Duncan Sands
3f329cb781 Teach GVN to also propagate switch cases. For example, in this code 
switch (n) {
    case 27:
      do_something(x);
    ...
  }
the call do_something(x) will be replaced with do_something(27).  In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 08:29:06 +00:00
Craig Topper
75fe5f3bab Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 07:02:24 +00:00
Craig Topper
1b526a98e3 Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 05:53:50 +00:00
Craig Topper
25f6dfd108 Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 05:35:38 +00:00
Jim Grosbach
bee5d2fac8 Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 22:04:05 +00:00
Jim Grosbach
7abb795635 Fix and clean up tests. Un-XFAIL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:32:50 +00:00
Jim Grosbach
d6f85098e1 Fix and clean up tests. Un-XFAIL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:28:30 +00:00
David Greene
2f0722c105 Make Test More Thorough 
Check that all ADD patters are processed.

Add a SUB test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141314 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 21:20:44 +00:00
Peter Collingbourne
5d5c0624d0 s/tblgen/llvm-tblgen/g in a few missed places, including the tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 13:39:59 +00:00
Torok Edwin
624c5edcd4 ocaml bindings: add llvm_ipo based on IPO.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 12:12:27 +00:00
Torok Edwin
0e68e90175 add more tests for the OCaml bindings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 12:12:12 +00:00