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Author SHA1 Message Date
Bill Wendling
de86beae7d Add mention of Glasgow Haskell Compiler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156648 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 21:42:37 +00:00
Chad Rosier
226ddf5278 [fast-isel] Add support for selecting @llvm.trap(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 21:33:49 +00:00
Brendon Cahoon
927ede5a87 Updated instruction table due to addded intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156644 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 21:10:16 +00:00
Sirish Pande
12a52525e8 Remove warnings from HexagonVLIWPacketizer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156636 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 20:00:34 +00:00
Duncan Sands
5abd10a394 Some release notes for dragonegg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156635 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:59:43 +00:00
Brendon Cahoon
6d532d8860 Hexagon constant extender support. 
Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:56:59 +00:00
Chad Rosier
e1093e5503 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156633 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:43:29 +00:00
Chad Rosier
2b3b335f2d [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:40:25 +00:00
Sirish Pande
81e900d14c Hexagon V5 intrinsics support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156631 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:39:13 +00:00
Jakob Stoklund Olesen
79e2045531 Defer computation of SuperRegs. 
Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:01:01 +00:00
Chad Rosier
2a2e9d54e9 [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg 
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 18:51:55 +00:00
Nuno Lopes
12c807873a objectsize: add a few more tests and fix a bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156625 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 18:25:29 +00:00
Chad Rosier
2f6ae41f14 [fast-isel] Rather then assert (or segfault in a non-asserts build), fall back 
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 17:41:06 +00:00
Chad Rosier
f4bd21c256 The return type is an unsigned, not a bool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 16:41:38 +00:00
Manman Ren
4949e98ccc Add space before an open parenthesis in control flow statements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 15:36:46 +00:00
Preston Gurd
3c579c8343 Added X86 Atom latencies to X86InstrMMX.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 14:27:12 +00:00
Stepan Dyatkovskiy
cb7a5f5f57 PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to include/llvm/Support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156613 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 10:34:23 +00:00
Hans Wennborg
12447575dc Fix test/CodeGen/X86/tls-pie.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156612 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 10:19:54 +00:00
Hans Wennborg
228756c744 Implement initial-exec TLS model for 32-bit PIC x86 
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 10:11:01 +00:00
Silviu Baranga
169e9ba2b2 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 09:28:27 +00:00
Silviu Baranga
ca3cd419a5 Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 09:10:54 +00:00
Rafael Espindola
383fd7afd9 Fix a use after free when the streamer is destroyed. Fixes pr12622. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156606 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 03:42:13 +00:00
Akira Hatanaka
2b7ab5eb49 Fix a misleading comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156603 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 01:45:15 +00:00
Jim Grosbach
2684d9e3c7 Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156602 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 01:41:30 +00:00
Jim Grosbach
639aa87bee Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156601 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 01:39:13 +00:00
Eli Friedman
5b6dfee28e Fix a minor logic mistake transforming compares in instcombine. PR12514. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156600 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 01:32:59 +00:00
Manman Ren
247c5ab07c ARM: peephole optimization to remove cmp instruction 
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 01:30:47 +00:00
Dan Gohman
d4347e1af9 Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(), 
but it generates int3 on x86 instead of ud2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 00:19:32 +00:00
Eric Christopher
61aef8bdf7 Allow unique_file to take a mode for file permissions, but default 
to user only read/write.

Part of rdar://11325849

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156591 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 00:07:44 +00:00
Chad Rosier
620ee81fa0 Fix intendation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156589 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 23:38:07 +00:00
Jakob Stoklund Olesen
fcad79671f Compute secondary sub-registers. 
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

  Q0_Q1 = [Q0, Q1],  Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 23:27:10 +00:00
Nuno Lopes
9d236f909c objectsize: add support for GEPs with non-constant indexes 
add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156585 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 23:17:35 +00:00
Preston Gurd
deaa3f3e52 Added X86 Atom latencies for instructions in X86InstrInfo.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:58:35 +00:00
Eric Christopher
05b7a50210 Add support for the 'X' inline asm operand modifier. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:48:22 +00:00
Andrew Trick
89c324bf11 misched: Print machineinstrs with -debug-only=misched 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:06:21 +00:00
Andrew Trick
28ebc89c41 misched: tracing register pressure heuristics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:06:19 +00:00
Andrew Trick
7196a8ff21 misched: Add register pressure backoff to ConvergingScheduler. 
Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.

WIP: This is mostly functional but untested and not likely to do much good yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:06:16 +00:00
Andrew Trick
16716c7302 misched: Release only unscheduled nodes into ReadyQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:06:14 +00:00
Andrew Trick
d38f87eeec misched: Added ReadyQ container wrapper for Top and Bottom Queues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:06:12 +00:00
Andrew Trick
7f8ab785af misched: Introducing Top and Bottom register pressure trackers during scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:06:10 +00:00
Sirish Pande
0cfb5cfe97 Hexagon V5 Support - V5 td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156569 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 20:24:28 +00:00
Sirish Pande
7517bbc91a Hexagon V5 FP Support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 20:20:25 +00:00
Andrew Trick
55ba5dff3c RegPressure: API for speculatively checking instruction pressure. 
Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the
tracker by speculatively handling an instruction out of order. But it
is convenient for now. In the future, we will cache each instruction's
pressure contribution to make this efficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156561 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 19:11:52 +00:00
Andrew Trick
d253035339 RegPressure: fix array index iteration style. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156560 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 19:11:49 +00:00
Dan Gohman
b401e3bd16 Teach DeadStoreElimination to eliminate exit-block stores with phi addresses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 18:57:38 +00:00
Manman Ren
fe65d98dad Revert: 156550 "ARM: peephole optimization to remove cmp instruction" 
This commit broke an external linux bot and gave a compile-time warning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 18:49:43 +00:00
Jakob Stoklund Olesen
148f392195 Precompute lists of explicit sub-registers and indices. 
The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 17:46:18 +00:00
Dan Gohman
ac84461e5a Rewrite ScalarEvolution::hasOperand to use an explicit worklist instead 
of recursion, to avoid excessive stack usage on deep expressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156554 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 17:21:30 +00:00
Nuno Lopes
e54874471c teach DSE and isInstructionTriviallyDead() about calloc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156553 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 17:14:00 +00:00
Joel Jones
9777f61bfe formatting change: strip debug info from test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156551 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 16:55:31 +00:00