Evan Cheng
cc9876124e
Promote vector AND, OR, and XOR
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27632 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 21:20:24 +00:00
Evan Cheng
41f6cbbeb2
Vector type promotion for ISD::LOAD and ISD::SELECT
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27606 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 16:33:18 +00:00
Chris Lattner
fdfded5588
Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27604 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 16:20:43 +00:00
Chris Lattner
9d956250f5
Don't memoize vloads in the load map! Don't memoize them anywhere here, let
...
getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27602 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 03:25:41 +00:00
Evan Cheng
98f8aeb45f
Only get Tmp2 for cases where number of operands is > 1. Fixed return void.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27586 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 06:33:39 +00:00
Chris Lattner
b49e52c7e2
add some todos
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27580 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 02:00:08 +00:00
Chris Lattner
f87324e44d
Add basic support for legalizing returns of vectors
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27578 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 01:31:51 +00:00
Jim Laskey
1069fbdd2f
Use existing information.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27574 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 23:09:19 +00:00
Evan Cheng
db3c626eb9
Missing break
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27559 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 18:54:36 +00:00
Chris Lattner
b22e35a3c3
Add code generator support for VSELECT
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27542 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 22:22:57 +00:00
Chris Lattner
17614ea63d
Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns
...
to match again :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27533 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 05:34:25 +00:00
Chris Lattner
3e104b1116
Codegen shufflevector as VVECTOR_SHUFFLE
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27529 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 04:15:24 +00:00
Chris Lattner
4ddd283f69
add a sanity check: LegalizeOp should return a value that is the same type
...
as its input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27528 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 04:13:17 +00:00
Evan Cheng
f6bf87f2cc
INSERT_VECTOR_ELT lowering bug:
...
store vector to $esp
store element to $esp + sizeof(VT) * index
load vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27517 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 01:46:37 +00:00
Chris Lattner
67f1351498
Stub out shufflevector
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27514 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 01:19:25 +00:00
Jim Laskey
f36e2d3415
Remove section change in function end, preventing override of function's real
...
section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27503 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 00:35:59 +00:00
Jim Laskey
6b92b8e50d
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27494 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-07 20:44:42 +00:00
Jim Laskey
4188699f80
Foundation for call frame information.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27491 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-07 16:34:46 +00:00
Evan Cheng
c04766a228
1. If both vector operands of a vector_shuffle are undef, turn it into an undef.
...
2. A shuffle mask element can also be an undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27472 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-06 23:20:43 +00:00
Chris Lattner
2e2ef95350
Make a vector live across blocks have the correct Vec type. This fixes
...
CodeGen/X86/2006-04-04-CrossBlockCrash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27436 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 06:54:42 +00:00
Evan Cheng
18dd6d0a2a
Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded
...
or custom lowering fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27432 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 06:07:11 +00:00
Chris Lattner
e44be60ee9
Do not create ZEXTLOAD's unless we are before legalize or the operation is
...
legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27402 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 17:39:18 +00:00
Chris Lattner
4352cc9e21
* Add supprot for SCALAR_TO_VECTOR operations where the input needs to be
...
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27399 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 17:23:26 +00:00
Chris Lattner
08da55eeff
Constant fold bitconvert(undef)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27391 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 01:02:22 +00:00
Chris Lattner
4672f71ac4
The stack alignment is now computed dynamically, just verify it is correct.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27380 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 21:39:57 +00:00
Chris Lattner
7dca8e2d73
Remove unused method
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27379 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 21:39:03 +00:00
Chris Lattner
97c2073270
Add a missing check, this fixes UnitTests/Vector/sumarray.c
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27375 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 17:29:28 +00:00
Chris Lattner
a4c5d8c6b4
Add a missing check, which broke a bunch of vector tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27374 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 17:21:50 +00:00
Andrew Lenharth
cf4fb61f6c
back this out
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27367 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-03 03:16:50 +00:00
Andrew Lenharth
50a0d426e8
This should be a win of every arch
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27364 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 21:42:45 +00:00
Chris Lattner
1b5232a937
relax assertion
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27358 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 06:19:46 +00:00
Chris Lattner
1482b5fc7a
Allow targets to compute masked bits for intrinsics.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27357 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 06:15:09 +00:00
Chris Lattner
350bec0fb9
Add a little dag combine to compile this:
...
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
%tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1]
%tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 ) ; <int> [#uses=1]
%tmp = seteq int %tmp, 0 ; <bool> [#uses=1]
%tmp3 = cast bool %tmp to int ; <int> [#uses=1]
ret int %tmp3
}
into this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
mtspr 256, r2
blr
instead of this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
xori r3, r3, 1
cntlzw r3, r3
srwi r3, r3, 5
mtspr 256, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27356 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 06:11:11 +00:00
Chris Lattner
4aab2f4ab5
Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27349 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 05:06:04 +00:00
Chris Lattner
bc70cf8be9
Implement the Expand action for binary vector operations to break the binop
...
into elements and operate on each piece. This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27347 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 03:57:31 +00:00
Chris Lattner
e58a780166
Intrinsics that just load from memory can be treated like loads: they don't
...
have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27346 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 03:41:14 +00:00
Chris Lattner
edab1b9133
Constant fold all of the vector binops. This allows us to compile this:
...
"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"
aka:
void %test2(<16 x sbyte>* %P) {
store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
ret void
}
into this:
_test2:
mfspr r2, 256
oris r4, r2, 32768
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
lvx v0, r5, r4
stvx v0, 0, r3
mtspr 256, r2
blr
instead of this:
_test2:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
vspltisb v0, 8
lvx v1, r5, r4
vxor v0, v1, v0
stvx v0, 0, r3
mtspr 256, r2
blr
... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27343 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 03:25:57 +00:00
Chris Lattner
5e46a19ec8
Add a new -view-legalize-dags command line option
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27342 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 03:07:27 +00:00
Chris Lattner
6258fb2592
Implement constant folding of bit_convert of arbitrary constant vbuild_vector nodes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27341 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 02:53:43 +00:00
Chris Lattner
5e08a11039
These entries already exist
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27340 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 02:51:27 +00:00
Chris Lattner
97d23335ad
Add some missing node names
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27339 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 02:41:18 +00:00
Chris Lattner
f8814cf8b8
Prefer larger register classes over smaller ones when a register occurs in
...
multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27334 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 00:24:45 +00:00
Chris Lattner
f1d0c623c6
Delete identity shuffles, implementing CodeGen/Generic/vector-identity-shuffle.ll
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27317 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 22:16:43 +00:00
Chris Lattner
c741ea424a
Do not endian swap split vector loads. This fixes UnitTests/Vector/sumarray-dbl on PPC.
...
Now all UnitTests/Vector/* tests pass on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27299 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 18:22:37 +00:00
Chris Lattner
d9731af75b
Do not endian swap the operands to a store if the operands came from a vector.
...
This fixes UnitTests/Vector/simple.c with altivec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27298 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 18:20:46 +00:00
Chris Lattner
29cd7db310
Remove dead *extloads. This allows us to codegen vector.ll:test_extract_elt
...
to:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 12, r32
;;
ldfs f8 = [r8]
mov ar.pfs = r3
br.ret.sptk.many rp
instead of:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 28, r32
adds r9 = 24, r32
adds r10 = 20, r32
adds r11 = 16, r32
;;
ldfs f6 = [r8]
;;
ldfs f6 = [r9]
adds r8 = 12, r32
adds r9 = 8, r32
adds r14 = 4, r32
;;
ldfs f6 = [r10]
;;
ldfs f6 = [r11]
ldfs f8 = [r8]
;;
ldfs f6 = [r9]
;;
ldfs f6 = [r14]
;;
ldfs f6 = [r32]
mov ar.pfs = r3
br.ret.sptk.many rp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27297 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 18:10:41 +00:00
Chris Lattner
e4b953939c
Delete dead loads in the dag. This allows us to compile
...
vector.ll:test_extract_elt2 into:
_test_extract_elt2:
lfd f1, 32(r3)
blr
instead of:
_test_extract_elt2:
lfd f0, 56(r3)
lfd f0, 48(r3)
lfd f0, 40(r3)
lfd f1, 32(r3)
lfd f0, 24(r3)
lfd f0, 16(r3)
lfd f0, 8(r3)
lfd f0, 0(r3)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27296 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 18:06:18 +00:00
Chris Lattner
1597221eac
Implement PromoteOp for VEXTRACT_VECTOR_ELT. Thsi fixes
...
Generic/vector.ll:test_extract_elt on non-sse X86 systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27294 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 17:55:51 +00:00
Chris Lattner
2ae2e98d4f
Scalarized vector stores need not be legal, e.g. if the vector element type
...
needs to be promoted or expanded. Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27293 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 17:37:22 +00:00
Chris Lattner
7e02151ce2
Make sure to pass enough values to phi nodes when we are dealing with
...
decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27280 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 02:12:18 +00:00