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17 Commits

Author SHA1 Message Date
Daniel Sanders
68de93c3b4 [mips] Add synci instruction. 
Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222899 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-27 17:28:10 +00:00
Vladimir Medic
afa6150f04 This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-03 13:12:59 +00:00
Akira Hatanaka
a796d90c0e [mips] Use ptr_rc to simplify definitions of base+index load/store instructions. 
Also, fix predicates.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 00:55:15 +00:00
Akira Hatanaka
83d8ef133b [mips] Fix FP branch instructions to have explicit FP condition code register 
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-26 20:13:47 +00:00
Akira Hatanaka
db8e0bbedb [mips] Increase the number of floating point control registers available to 32. 
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-01 20:31:44 +00:00
Chad Rosier
096c0a0331 [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg 
function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-26 22:23:32 +00:00
Nico Rieck
ef1762b6a1 Use object file specific section type for initial text section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-14 21:18:36 +00:00
Akira Hatanaka
94e36e34e2 Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck. 
Patch by Vladimir Medic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160143 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-12 21:19:32 +00:00
Akira Hatanaka
241b77fa45 Reapply r158846. 
Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 18:46:47 +00:00
Akira Hatanaka
63d10fbc89 revert r159851. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-06 20:16:48 +00:00
Akira Hatanaka
e32cc0d545 Reapply r158846. 
Include file MipsGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-06 19:29:11 +00:00
Akira Hatanaka
02a227af91 Revert r158846. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 21:19:39 +00:00
Akira Hatanaka
b66510f309 In MipsDisassembler.cpp, instead of defining register class tables, use the ones 
that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.

Also, fix bug in function DecodeAFGR64RegisterClass.

Patch by Vladimir Medic. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 20:39:23 +00:00
Akira Hatanaka
ecdc9d5bb2 Add disassembler to MIPS. 
Patch by Vladimir Medic. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-17 18:03:21 +00:00
Akira Hatanaka
9dd16d41a2 Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 03:01:13 +00:00
Akira Hatanaka
02365945a6 Revert r153924. There were buildbot failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 02:51:09 +00:00
Akira Hatanaka
885020a7a7 MIPS disassembler support. 
Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 02:20:58 +00:00