Commit Graph

26819 Commits

Author SHA1 Message Date
Matt Arsenault
3560dd2dcd R600/SI: Fix moveToVALU when the first operand is VSrc.
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:55 +00:00
Matt Arsenault
9bc4b2c0da R600/SI: Fix multiple SGPR reads when using VCC.
No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:50 +00:00
Matt Arsenault
e64a289609 R600/SI: Implement add i64, but do not yet enable.
Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:47 +00:00
Matt Arsenault
15703e0a71 R600/SI: Specify SSrc operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195039 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:43 +00:00
Matt Arsenault
f38be91a82 R600/SI: addc / adde i32 are legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195038 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:40 +00:00
Matt Arsenault
b2254e603d R600/SI: Match addc to S_ADD_U32.
The carry always goes to SCC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195037 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:37 +00:00
Matt Arsenault
62f35fb926 R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:34 +00:00
Matt Arsenault
f53b7841a1 R600/SI: Specify S_ADD/S_SUB set SCC and add is commutable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:32 +00:00
Matt Arsenault
3e38856f04 R600/SI: Move patterns to match add / sub to scalar instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:29 +00:00
Matt Arsenault
836c5133c6 R600/SI: Fix extra defs of VCC / SCC.
When replacing scalar operations with vector,
the wrong implicit output register was used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:21 +00:00
Tom Stellard
b570599c8f R600: Enable the IR structurizer by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195031 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:44 +00:00
Tom Stellard
44248e0f63 R600: Fix a crash in the AMDILCFGStrucurizer
The ifPatternMatch() function was not correctly reporting the number
of matches in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:38 +00:00
Tom Stellard
ef37e453c4 R600: Add a SubtargetFeatture for disabling the ifcvt pass.
This is useful when writing test cases for the AMDIL structurizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195029 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:33 +00:00
Tom Stellard
b4c3516b0f R600: Use lower-case for EnableIRStructurizer feature
llc converts all values passed to -mattr= to lowercase, so this
enables us to toggle this feature when using llc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:29 +00:00
Tom Stellard
204c953cd5 R600/SI: Fix illegal VGPR->SGPR copy inside of loop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 18:50:20 +00:00
Tom Stellard
bf9ddd5e8f R600/SI: Fix another case of illegal VGPR->SGPR copy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 18:50:15 +00:00
Daniel Sanders
23427207ea [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code for (ConstantFP 0.0)
Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64
which resulted in an impossible constraint on the register allocation. It now
uses BuildPairF64_64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:12:43 +00:00
Matheus Almeida
26651c7a66 [mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:09:54 +00:00
Matheus Almeida
95adf91f29 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 12:32:49 +00:00
Alexey Samsonov
b21ab43cfc Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
  Base *foo = new Child();
  delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 09:31:53 +00:00
Kevin Qin
69b2447b6a [AArch64 NEON]Add mov alias for simd copy instructions.
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 09:20:32 +00:00
Hao Liu
97577757c6 Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.
The functions are like: vst1_s8_x2 ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 06:31:53 +00:00
Andrew Trick
bb756ca244 Added a size field to the stack map record to handle subregister spills.
Implementing this on bigendian platforms could get strange. I added a
target hook, getStackSlotRange, per Jakob's recommendation to make
this as explicit as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-17 01:36:23 +00:00
Juergen Ributzka
0ccb37a733 The WebKit_JS CC preserves the same registers as the C CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194936 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 22:08:58 +00:00
Vincent Lejeune
4110797853 R600: Make dot_4 instructions predicable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 16:24:41 +00:00
Jim Grosbach
35de9946d5 X86: Encode the 'h' cpu subtype in the MachO header for x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194906 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 00:52:57 +00:00
Ana Pazos
a53bf06f7a Implemented aarch64 Neon scalar vmulx_lane intrinsics
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 23:32:10 +00:00
Lang Hames
445fd04f53 Remove unused arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 23:19:01 +00:00
Lang Hames
8c66df2c7a During folding for patchpoint/stackmap instructions, defer creation of new MIs
until we know that folding will be successful.

No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194880 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 23:13:21 +00:00
Juergen Ributzka
5a364c5561 [weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 22:34:48 +00:00
Matt Arsenault
c3ec7e2273 Make method static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194858 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 22:02:28 +00:00
Chad Rosier
5758c3c832 [AArch64] Fix the scalar NEON ACLE functions so that they return float/double
rather than the vector equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194853 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 21:28:10 +00:00
Bob Wilson
cc7052343e Avoid illegal integer promotion in fastisel
Stop folding constant adds into GEP when the type size doesn't match.
Otherwise, the adds' operands are effectively being promoted, changing the
conditions of an overflow.  Results are different when:

    sext(a) + sext(b) != sext(a + b)

Problem originally found on x86-64, but also fixed issues with ARM and PPC,
which used similar code.

<rdar://problem/15292280>

Patch by Duncan Exon Smith!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194840 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 19:09:27 +00:00
Tom Stellard
5cddda6d13 R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()
This fixes a crash with GNOME settings manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 18:26:45 +00:00
Cameron McInally
28e12e9f02 Add AVX512 unmasked FMA intrinsics and support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 17:01:14 +00:00
Daniel Sanders
cb85ded998 [mips][msa] lowerMSABitClear() should use SelectionDAG::getNOT() instead of using a long-winded equivalent.
Now that getConstant(-1, MVT::v2i64) works correctly on MIPS32 we can use
SelectionDAG::getNOT() to produce the bitmask.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 16:02:04 +00:00
Alexey Samsonov
4215561768 Hopefully fix uninitialized memory read in AArch64AsmParser found by MSan bootstrap bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194818 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 15:49:30 +00:00
Daniel Sanders
ea28aafa83 Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 type
Summary:
When getConstant() is called for an expanded vector type, it is split into
multiple scalar constants which are then combined using appropriate build_vector
and bitcast operations.

In addition to the usual big/little endian differences, the case where the
element-order of the vector does not have the same endianness as the elements
themselves is also accounted for.  For example, for v4i32 on big-endian MIPS,
the byte-order of the vector is <3210,7654,BA98,FEDC>. For little-endian, it is
<0123,4567,89AB,CDEF>.
Handling this case turns out to be a nop since getConstant() returns a splatted
vector (so reversing the element order doesn't change the value)

This fixes a number of cases in MIPS MSA where calling getConstant() during
operation legalization introduces illegal types (e.g. to legalize v2i64 UNDEF
into a v2i64 BUILD_VECTOR of illegal i64 zeros). It should also handle bigger
differences between illegal and legal types such as legalizing v2i64 into v8i16.

lowerMSASplatImm() in the MIPS backend no longer needs to avoid calling
getConstant() so this function has been updated in the same patch.

For the sake of transparency, the steps I've taken since the review are:
* Added 'virtual' to isVectorEltOrderLittleEndian() as requested. This revealed
  that the MIPS tests were falsely passing because a polymorphic function was
  not actually polymorphic in the reviewed patch.
* Fixed the tests that were now failing. This involved deleting the code to
  handle the MIPS MSA element-order (which was previously doing an byte-order
  swap instead of an element-order swap). This left
  isVectorEltOrderLittleEndian() unused and it was deleted.
* Fixed build failures caused by rebasing beyond r194467-r194472. These build
  failures involved the bset, bneg, and bclr instructions added in these commits
  using lowerMSASplatImm() in a way that was no longer valid after this patch.
  Some of these were fixed by calling SelectionDAG::getConstant() instead,
  others were fixed by a new function getBuildVectorSplat() that provided the
  removed functionality of lowerMSASplatImm() in a more sensible way.

Reviewers: bkramer

Reviewed By: bkramer

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194811 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 12:56:49 +00:00
Justin Holewinski
4d748eb0e4 [NVPTX] Fix handling of indirect calls
Using a special machine node is cleaner than an InlineAsm node, and fixes an assertion failure in InstrEmitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194810 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 12:30:04 +00:00
Zoran Jovanovic
42cb3abadd Use instr mapping for microMIPS in llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 08:07:34 +00:00
Matt Arsenault
509a492442 Add target hook to prevent folding some bitcasted loads.
This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)

On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.

Patch by Micah Villmow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 04:42:23 +00:00
Peter Zotov
e016a163e9 [llvm-c] Make LLVMGetTargetFromName actually work
LLVMGetTargetFromName used to compare two char* strings directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 02:51:18 +00:00
Peter Zotov
fa74752298 [llvm-c] Add missing const qualifiers to LLVMCreateTargetMachine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 02:51:12 +00:00
Peter Zotov
5ea0c20ce7 [llvm-c] Simplify signature of LLVMGetTargetFromName
LLVMGetTargetFromName was not yet present in an LLVM release,
so this does not break compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 02:51:01 +00:00
Reed Kotler
1703a71495 Make all the conditional Mips 16 branches get initially set for the
short form. Constant islands will expand them if they are out of range.
Since there is not direct object emitter at this time, it does not
have any material affect because the assembler sorts this out. But we
need to know for the actual constant island work. We track the difference
by putting # 16 inst in the comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 02:21:52 +00:00
Matt Arsenault
59d3ae6cdc Add addrspacecast instruction.
Patch by Michele Scandale!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 01:34:59 +00:00
Tom Stellard
19a99df130 R600: Fix scheduling of instructions that use the LDS output queue
The LDS output queue is accessed via the OQAP register.  The OQAP
register cannot be live across clauses, so if value is written to the
output queue, it must be retrieved before the end of the clause.
With the machine scheduler, we cannot statisfy this constraint, because
it lacks proper alias analysis and it will mark some LDS accesses as
having a chain dependency on vertex fetches.  Since vertex fetches
require a new clauses, the dependency may end up spiltting OQAP uses and
defs so the end up in different clauses.  See the lds-output-queue.ll
test for a more detailed explanation.

To work around this issue, we now combine the LDS read and the OQAP
copy into one instruction and expand it after register allocation.

This patch also adds some checks to the EmitClauseMarker pass, so that
it doesn't end a clause with a value still in the output queue and
removes AR.X and OQAP handling from the scheduler (AR.X uses and defs
were already being expanded post-RA, so the scheduler will never see
them).

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 00:12:45 +00:00
Tom Stellard
bdbcffa4af R600/SI: Add processor type for Hawaii
Patch by: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194752 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 23:46:00 +00:00
Matt Arsenault
25116f5096 R600/SI: Remove redundant legalizeOperands call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194749 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 23:44:25 +00:00
Hans Wennborg
ba0e1ee030 Add #include raw_ostream.h in lib/Target/R600/SIFixSGPRCopies.cpp
This was casuing my release+asserts build on Windows to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 23:24:09 +00:00