Commit Graph

13472 Commits

Author SHA1 Message Date
Jim Grosbach
37ee464ea9 Destination register operand is optional for ADC and SBC ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:57:17 +00:00
Jim Grosbach
e8606dc7c8 Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:50:29 +00:00
Bruno Cardoso Lopes
61905f0139 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 01:15:33 +00:00
Evan Cheng
e721f5c8d3 Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 00:42:17 +00:00
Jim Grosbach
dc89561fec Add check for predicate w/o S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 16:25:04 +00:00
Jim Grosbach
92bf81ddd0 Improve test cases from r134746.
Use memory barriers to force if-conversion off for these tests instead of
the internal llc command line option ifcvt-limit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 16:06:01 +00:00
Andrew Trick
b9484cafcc Comment correction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 03:39:22 +00:00
Jim Grosbach
3f00e31706 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 17:09:57 +00:00
Jim Grosbach
589130fac1 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:48:36 +00:00
NAKAMURA Takumi
fecdc98390 test/CodeGen/PowerPC/vector.ll: Tweak redirection >%t >%t to >%t >>%t. See also r134814 (test/CodeGen/X86/vector.ll).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:21:52 +00:00
Cameron Zwarich
ce3a9f51ce Add a missing test for r134882.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 08:35:17 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:57:24 +00:00
Rafael Espindola
b5a12dd12f Don't duplicate the work done by a gep into a "bitcast" if the gep has
more than one use.

Fixes PR10322.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134883 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:43:47 +00:00
Rafael Espindola
aecfdd3068 Move the loads after the calls so that the fix for
PR10292 doesn't show that the loads don't alias
the allocas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 23:53:58 +00:00
Rafael Espindola
4fe509431b Use CHECK-NEXT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 22:56:50 +00:00
Nick Lewycky
b4f6095bae Remove tests for APIs that were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 18:55:51 +00:00
Chris Lattner
1afcace3a3 Land the long talked about "type system rewrite" patch. This
patch brings numerous advantages to LLVM.  One way to look at it
is through diffstat:
 109 files changed, 3005 insertions(+), 5906 deletions(-)

Removing almost 3K lines of code is a good thing.  Other advantages
include:

1. Value::getType() is a simple load that can be CSE'd, not a mutating
   union-find operation.
2. Types a uniqued and never move once created, defining away PATypeHolder.
3. Structs can be "named" now, and their name is part of the identity that
   uniques them.  This means that the compiler doesn't merge them structurally
   which makes the IR much less confusing.
4. Now that there is no way to get a cycle in a type graph without a named
   struct type, "upreferences" go away.
5. Type refinement is completely gone, which should make LTO much MUCH faster
   in some common cases with C++ code.
6. Types are now generally immutable, so we can use "Type *" instead 
   "const Type *" everywhere.

Downsides of this patch are that it removes some functions from the C API,
so people using those will have to upgrade to (not yet added) new API.  
"LLVM 3.0" is the right time to do this.

There are still some cleanups pending after this, this patch is large enough
as-is.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 17:41:24 +00:00
Chris Lattner
5445ecdf69 more tests not making the jump into the brave new world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:57:10 +00:00
Chris Lattner
ca5470c99d remove some crufy old tests that aren't adding much value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:55:16 +00:00
Chris Lattner
5fe319b3bd remove a test that doesn't make sense in the new world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:52:42 +00:00
NAKAMURA Takumi
9eb36758ac test/CodeGen/X86/vector.ll: Tweak temporary output to appease Win32 hosts.
With Lit (not bash) in a test, multiple redirects >%t might open(%t, "w") multiple. It can be avoided if latter redirect is >>%t.

It might work even if ">/dev/null" were used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 10:22:28 +00:00
Lang Hames
f86a547419 Added test cases for GVN signed intrinsics recognition, r134777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134778 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 00:36:54 +00:00
Jakob Stoklund Olesen
56573cc1ae Hoist spills within a basic block.
Try to move spills as early as possible in their basic block. This can
help eliminate interferences by shortening the live range being
spilled.

This fixes PR10221.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 00:25:03 +00:00
Evan Cheng
3286920505 Add support for ARM / Thumb mode switching with .code 16 and .code 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:36:29 +00:00
Evan Cheng
f0b3c12919 Fix broken x86_64 tests which specify non-64-bit cpu's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:29:33 +00:00
Eli Friedman
f06ff4eae3 Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134753 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:16:47 +00:00
Jim Grosbach
25e6d48220 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:50:04 +00:00
Julien Lerouge
f29608267b Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:40:25 +00:00
Cameron Zwarich
33390848a7 Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:39:21 +00:00
Jakob Stoklund Olesen
51458ed09e Be more aggressive about following hints.
RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.

To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.

Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.

Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 20:46:18 +00:00
Jim Grosbach
245f5e8e2a Use ARMPseudoExpand for ARM tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 18:50:22 +00:00
Benjamin Kramer
9c64030445 Emit a more efficient magic number multiplication for exact sdivs.
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

  struct foo { char x[24]; };
  long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  sarl	$3, %eax
  imull	$-1431655765, %eax, %eax
instead of
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  movl	$715827883, %ecx
  imull	%ecx
  movl	%edx, %eax
  shrl	$31, %eax
  sarl	$2, %edx
  addl	%eax, %edx
  movl	%edx, %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134695 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 10:31:30 +00:00
Lang Hames
1fb0955cab Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 01:50:54 +00:00
Jakob Stoklund Olesen
2aa6b4c142 Fix more register allocation sensitive tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:24:06 +00:00
Jakob Stoklund Olesen
caab27963b Remove a test that no longer makes sense.
It was testing a linear scan feature:

  Test if linearscan is unfavoring registers for allocation to allow
  more reuse of reloads from stack slots.

The greedy register allocator doesn't access any stack slots in this
function, so the linear scan feature was not being tested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:24:03 +00:00
Nick Lewycky
9bf45d0b1a Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:19:27 +00:00
Eric Christopher
77ed1353bf Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.

Fixes PR9675 and rdar://9740801


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:04:56 +00:00
Eric Christopher
31b5f00c4e Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://9738585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 22:29:07 +00:00
Evan Cheng
18fb1d35db Add Mode64Bit feature and sink it down to MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 21:06:52 +00:00
Evan Cheng
39dfb0ff84 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 03:55:05 +00:00
Lang Hames
d0626aacca Added a testcase for PR10220.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134573 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:36:02 +00:00
Andrew Trick
037d1c0c7e indvars -disable-iv-rewrite: Added SimplifyCongruentIVs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134530 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 20:50:43 +00:00
Tobias Grosser
df7102b7d6 LICM: Do not loose alignment on promotion
The promotion code lost any alignment information, when hoisting loads and
stores out of the loop. This lead to incorrect aligned memory accesses. We now
use the largest alignment we can prove to be correct.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 19:19:55 +00:00
Jakub Staszak
9da9934e27 Introduce "expect" intrinsic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 18:22:43 +00:00
Kevin Enderby
d7c7e2ff7d Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 17:55:20 +00:00
Kevin Enderby
d521f2d2f1 Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 17:23:46 +00:00
Dan Gohman
211f53aa04 Revert r134366 and add an explicit triple to make this test host-independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 22:09:19 +00:00
Eli Friedman
af45b3d8cb Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 18:21:20 +00:00
Jakob Stoklund Olesen
9693d4c3f0 Fix PR10277.
Remat during spilling triggers dead code elimination. If a phi-def
becomes unused, that may also cause live ranges to split into separate
connected components.

This type of splitting is different from normal live range splitting. In
particular, there may not be a common original interval.

When the split range is its own original, make sure that the new
siblings are also their own originals. The range being split cannot be
used as an original since it doesn't cover the new siblings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 15:38:41 +00:00
Benjamin Kramer
fc87cdc1f4 PR10267: Don't combine an equality compare with an AND into an inequality compare when the AND has more than one use.
This can pessimize code, inequalities are generally more expensive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134379 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-04 20:16:36 +00:00