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Author SHA1 Message Date
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 00:01:06 +00:00
Dan Gohman
3335a22a37 Make this code less confusing. Instead of reassigning BB, just operate 
on the original variables, so it's easier to see what is being done
to which blocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102759 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 20:14:26 +00:00
Dan Gohman
71edb241a1 Remove the -disable-16bit command-line option, which is now obsolete. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 18:30:26 +00:00
Evan Cheng
1361796dd0 Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-30 01:12:32 +00:00
Dan Gohman
ffce6f1343 Don't leave Base.FrameIndex uninitialized, so that it doesn't 
print randomly in debug output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102668 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 23:30:41 +00:00
Devang Patel
67a444ca36 Print variable scope name in DEBUG_VALUE comment. Useful in some cases. e.g. 
##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
	##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
	##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
	##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
	##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102655 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 18:52:10 +00:00
Evan Cheng
3f54c64a98 Load folding tail call should not use ebp / rbp after it's popped. PEI 
should use esp / rsp to reference frame instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 05:08:22 +00:00
Evan Cheng
8601a3d4de Frame index can be negative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 01:13:30 +00:00
Kevin Enderby
9ac7282117 Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the 
Operand size override prefix to be part of their records.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102556 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 23:20:40 +00:00
Jakob Stoklund Olesen
7261fb2a6f Teach X86FloatingPoint that a register can be killed multiple times by the same 
instruction.

This instruction would crash the pass:

  INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>

Now it doesn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 18:28:37 +00:00
Evan Cheng
2bce5f4b56 Enable i16 to i32 promotion by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 08:30:49 +00:00
Evan Cheng
39cfeecae5 Unbreak the build. Only form shld / shrd after legalization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 02:25:18 +00:00
Devang Patel
28ff35d030 Emit debug info for byval parameters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102486 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:39:28 +00:00
Evan Cheng
8b1190a540 Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 01:18:01 +00:00
Stuart Hastings
5a6a65be46 Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102477 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 00:35:10 +00:00
Evan Cheng
1c45acf510 Fix obvious typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102467 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 21:46:03 +00:00
Evan Cheng
b3716e3e28 SRA promotion is also not free. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-27 19:48:31 +00:00
Chris Lattner
ee9eb411ff on darwin empty functions need to codegen into something of non-zero length, 
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:37:21 +00:00
Evan Cheng
552f09a0d7 Promoting 16-bit cmp / test aren't free. Don't do it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 19:06:11 +00:00
Evan Cheng
fc4d530ad6 Remove a redundant comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 08:16:57 +00:00
Evan Cheng
962021bc7f - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. 
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:38:55 +00:00
Dale Johannesen
f822e733af Stop abusing EmitInstrWithCustomInserter for target-dependent 
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-25 21:33:54 +00:00
Evan Cheng
c82c20b315 Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-24 04:44:57 +00:00
Stuart Hastings
e3ff9ba40c Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 19:03:32 +00:00
Evan Cheng
2808ccb775 Fix X86ISD::CMP i16 to i32 promotion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-23 18:21:16 +00:00
Dan Gohman
f81eca0ab9 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel 
and into SelectionDAGBuilder and FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 20:46:50 +00:00
Evan Cheng
07c4e1085d - It's not safe to promote rotates (at least not trivially). 
- Some code refactoring.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102111 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 20:19:46 +00:00
Evan Cheng
e566763b19 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 03:18:23 +00:00
Evan Cheng
5528e7bcb1 isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:47:12 +00:00
Evan Cheng
fe5dcbc27d Trim include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101978 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:39:06 +00:00
Bill Wendling
a040fffefb Handle a displacement location in 64-bit as an RIP-relative displacement. It 
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:

target triple = "x86_64-apple-darwin"

define double @func(double %a) {
  %tmp1 = fmul double %a, 5.000000e-01            ; <double> [#uses=1]
  ret double %tmp1
}

define i32 @main() nounwind {
  %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
  ret i32 0
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101965 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 00:34:04 +00:00
Chris Lattner
d6139425f5 teach the x86 address matching stuff to handle 
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 23:18:40 +00:00
Dale Johannesen
7609017dc3 Because of the EMMS problem, right now we have to support 
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 22:34:09 +00:00
Chris Lattner
d7aba875c1 disable optimizations in this directory for MSVC9. This avoids 
an optimizer infinite loop on the file, PR6866.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 01:11:32 +00:00
Eric Christopher
6d972fd087 Remove the palignr intrinsics now that we lower them to vector shuffles, 
shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 00:59:54 +00:00
Evan Cheng
4c26e93e89 More progress on promoting i16 operations to i32 for x86. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 19:29:22 +00:00
Chris Lattner
eef6d78be1 teach the x86 asm parser how to handle segment prefixes 
in memory operands.  rdar://7874844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 18:56:34 +00:00
Chris Lattner
89f94926b0 remove a dead variable, PR6856 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 17:28:00 +00:00
Dan Gohman
0d805c33d1 Add const qualifiers to TargetLoweringObjectFile usage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 16:44:48 +00:00
Dan Gohman
82d5eaf23e Use const_cast instead of a C-style cast to cast away const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101639 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 16:43:55 +00:00
Dan Gohman
d858e90f03 Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 15:26:15 +00:00
Dan Gohman
1e93df6f0b Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 14:41:14 +00:00
Chris Lattner
65de1b9eb3 a bunch of ssse3 instructions are misencoded to think they have an 
i8 field when they really do not.  This fixes rdar://7840289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 07:38:24 +00:00
Evan Cheng
e5b51ac770 More work to allow dag combiner to promote 16-bit ops to 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-17 06:13:15 +00:00
Eric Christopher
551754c495 Revert 101465, it broke internal OpenGL testing. 
Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101579 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 23:37:20 +00:00
Dan Gohman
53c5e42ab9 Add skeleton target-specific SelectionDAGInfo files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101564 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 23:04:22 +00:00
Chris Lattner
aef1fea3d3 add a missing break back, patch by Nico Schmidt! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101538 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 21:15:15 +00:00
Dan Gohman
37f32ee7ff Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 20:11:05 +00:00
Gabor Greif
4ec2258ffb reapply r101434 
with a fix for self-hosting

rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 15:33:14 +00:00
Evan Cheng
64b7bf71e8 Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding. 
x86 support is off by default. It can be enabled with -promote-16bit.

Work in progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-16 06:14:10 +00:00