laid out closer to the VM so that calls to library functions (e.g. puts()) and
callback (e.g. JITResolver::CompilationCallback) fit into 30 bits of the call
instruction.
* Abort if architecture is not yet supported (not X86 or Sparc) because it
likely requires a different set of parameters to mmap() .
* Stop using hard-coded values for page size; use sysconf(_SC_PAGESIZE) instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6610 91177308-0d34-0410-b5e6-96231b3b80d8
the loop, and in both cases. In the first case, it is a VReg that is a constant
so it may be actually converted to a constant. In the second case, it is already
a constant, but then if it doesn't change its type (e.g. to become a register
and have the value loaded from memory if it is too large to live in its
instruction field), we must change the opcode BEFORE the 'continue', otherwise
we miss the opportunity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6602 91177308-0d34-0410-b5e6-96231b3b80d8
rewriting it. I also vacuumed out all the commented-out code and
inaccurate comments, etc.
(We need to put the mapping information in a data structure so that we can
pass it out to the JIT, instead of automagically converting it to .byte
directives.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6574 91177308-0d34-0410-b5e6-96231b3b80d8
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6564 91177308-0d34-0410-b5e6-96231b3b80d8
* Labeled sections that are not currently used in the Sparc backend as not
requiring completion at this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6562 91177308-0d34-0410-b5e6-96231b3b80d8
* Added instruction classes which start building from rs1, then rs2, and rd.
* Fixed order of operands in classes 4.1 and 4.2; added 4.6 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6561 91177308-0d34-0410-b5e6-96231b3b80d8
* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6560 91177308-0d34-0410-b5e6-96231b3b80d8
This pass should be moved to lib/Target/Sparc since it's sparc specific
It also needs a file comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6553 91177308-0d34-0410-b5e6-96231b3b80d8
In particular these classes are the last that link the noncopyable classes
with the hash_map, vector, and list classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6552 91177308-0d34-0410-b5e6-96231b3b80d8
None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6549 91177308-0d34-0410-b5e6-96231b3b80d8
SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
requires a register-version opcode.
SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6548 91177308-0d34-0410-b5e6-96231b3b80d8
* No more createX86Emitter() vs. createSparcEmitter() -- there can be only one
* As a result, the memory management semantics must be handled according to
platform -- the parameters to mmap() are particularly sensitive to the host
architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6527 91177308-0d34-0410-b5e6-96231b3b80d8
