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13521 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
3aaa010ece Add AVX 128-bit sqrt versions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 17:51:40 +00:00
Nick Lewycky
b8c129ea66 Delete empty unused file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135379 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 05:54:06 +00:00
Eric Christopher
af37cb53f4 More minor adjustments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 07:28:35 +00:00
Eli Friedman
7105259ce8 Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 02:41:28 +00:00
Bruno Cardoso Lopes
4201ecae92 Add AVX 128-bit patterns for sint_to_fp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 00:50:20 +00:00
Eric Christopher
465c7aa97b Finish propagating %asmtmp->%1 change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 00:26:07 +00:00
Chris Lattner
7305c55a80 fix rdar://9776316 - type remapping needed for inline asm blobs, 
fixing some objc llvm-test crashes with LTO.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 23:18:40 +00:00
Bruno Cardoso Lopes
5bc37dd131 Fix a couple of things: 
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.

2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.

3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.

4) Tidy up code to be more clear and explicit about AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 22:24:33 +00:00
Eli Friedman
5232cc675c PR10370: Make sure we know how to relax push correctly on x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 21:28:39 +00:00
Chad Rosier
72d6f34af1 A real testcase for r135286. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135299 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 20:58:38 +00:00
Eric Christopher
d03ed6b8e7 Update these tests, no longer outputting names for the variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 20:58:16 +00:00
Chad Rosier
96a7db084f Add testcase for r135286. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 19:06:58 +00:00
Owen Anderson
43967a97cf Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 18:46:47 +00:00
Jim Grosbach
33c16a2737 ARM diagnostic when 's' suffix on mnemonic that can't set flags. 
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 22:04:21 +00:00
Jim Grosbach
70d8fcfaa0 Add some testcases for ARM MLA/MLS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:43:05 +00:00
Jim Grosbach
c8ae39e746 ARM MCRR/MCRR2 immediate operand range checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:26:42 +00:00
Jim Grosbach
e540c7422c ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:19:17 +00:00
Jim Grosbach
1134be2428 Enable some tests we now handle correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135185 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:02:23 +00:00
Eric Christopher
5427edeb68 Check register class matching instead of width of type matching 
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 20:13:52 +00:00
Bruno Cardoso Lopes
62f67f86fe Add 256-bit load/store recognition and matching in several places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:50:58 +00:00
Jim Grosbach
3b14a5c546 Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:35:38 +00:00
Jim Grosbach
791feea100 ARM ISB assembly parsing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:02:25 +00:00
Jim Grosbach
9dec507ecb ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:00:31 +00:00
Eric Christopher
2b88e8fbfe Add a testcase for r135123. 
Part of rdar://9761830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 06:23:09 +00:00
Benjamin Kramer
3ff25514ce Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 01:38:42 +00:00
Jim Grosbach
00a66653cb ARM tests for EOR instruction parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:22:21 +00:00
Jim Grosbach
6a86feafa8 Remove duplicate tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:19:19 +00:00
Jim Grosbach
e77494e3e3 ARM Assembler support for DSB instruction. 
Add instalias for default 'sy' option. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:18:13 +00:00
Jim Grosbach
032434d622 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 23:40:38 +00:00
Jim Grosbach
6f9f884502 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:59:38 +00:00
Bruno Cardoso Lopes
53c95880f0 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:28:55 +00:00
Jim Grosbach
14ab1c3387 ARM parsing and encoding tests for CMN/CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:26:58 +00:00
Jim Grosbach
d986bc66bc Shuffle ARM assembly tests a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:19:10 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
466b022c99 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more 
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:36:51 +00:00
Eli Friedman
2a01946de4 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. 
<rdar://problem/9763308>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:29:53 +00:00
Jim Grosbach
9bb098ad3a Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:14:23 +00:00
Jim Grosbach
f333d471d2 Testcases for ARM assembly BX/BXJ instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:25:46 +00:00
Jim Grosbach
37023b05c8 Testcases for ARM assembly BLX/BL instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:11:04 +00:00
Jim Grosbach
fff76ee7ef Range checking for 16-bit immediates in ARM assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:10:10 +00:00
Evan Cheng
3fd6e755d0 Change test case, one that actually failed before my commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:19:44 +00:00
Jim Grosbach
21101d60ce Add tests for ARM parsing of 'BKPT' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:17:36 +00:00
Jim Grosbach
76cbe02cdd Fix copy-pasto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:16:30 +00:00
Jim Grosbach
e52240c370 Add tests for ARM parsing of 'BIC' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:12:32 +00:00
Jim Grosbach
7ed6d22e96 Add some FIXMEs. 
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:10:23 +00:00
Evan Cheng
93a635c82c It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is another use of sqrt. rdar://9763193 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135058 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:08:16 +00:00
Jim Grosbach
59642c2600 Add tests for ARM parsing of 'AND' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:55:14 +00:00
Jim Grosbach
19906729a4 Improve ARM assembly parsing diagnostics a bit. 
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:49:30 +00:00
Jim Grosbach
da9f278c74 Add tests for ARM parsing of 'ADD' instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 18:12:46 +00:00
Jim Grosbach
37ee464ea9 Destination register operand is optional for ADC and SBC ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 17:57:17 +00:00