not just an Instruction*, at least in one unfortunate case:
the first operand to the va_arg instruction.
Modify ValueToDefVecMap to map from Value*, not Instruction*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7052 91177308-0d34-0410-b5e6-96231b3b80d8
preallocated. While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.
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Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
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so additional dep. edges have to be added.
This was needed to correctly handle conditional move instructions!
MachineCodeForBasicBlock is now an annotation on BasicBlock.
Renamed "earliestForNode" to "earliestReadyTimeForNode".
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class. The Method class is obsolete (renamed) and all references to it
are being converted over to Function.
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since some m. instr. may be generated by LLVM instrs. in other blocks.
Handle non-SSA (anti and output) edges and true edges uniformly by
working with machine instructions alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1269 91177308-0d34-0410-b5e6-96231b3b80d8
This wasn't a problem until we started putting copies for Phi values
that produced cycles in the SchedGraph!
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are now found as part of the initial walk of the machine code).
Also memory load/store instructions can be generated for non-memory
LLVM instructions, which wasn't handled before. It is now.
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Avoids having to handle some special cases that cause complex interactions
with instr. selection.
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(b) any instructions that use or set CC registers. Whether or not the
latter are needed really should be machine-dependent.
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(1) Add edges for Values that are written by multiple m/c instructions
(2) Add edges for LLVM operands that are not machine operands (e.g., Call args)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@676 91177308-0d34-0410-b5e6-96231b3b80d8
Value to a vector instead of a list.
Move SchedGraph.h & SchedPriorities.h into lib/CodeGen/InstrScheduling
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Move files from lib/CodeGen/TargetMachine to lib/Target
Move TargetData.h and TargetMachine.h to Target/{Data.h|Machine.h}
Prepare to split TargetMachine.h into several smaller files
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