Commit Graph

84539 Commits

Author SHA1 Message Date
Simon Atanasyan
3b4998fd8b Support MIPS DSP Rev2 intrinsics.
The patch reviewed by Akira Hatanaka.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162668 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 12:29:01 +00:00
NAKAMURA Takumi
1ba64859f5 llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on non-x86 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 11:50:26 +00:00
NAKAMURA Takumi
83e2546ad3 DWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 10:10:10 +00:00
NAKAMURA Takumi
fdc35405cd llvm/test/CodeGen/X86/fma_patterns.ll: Add -mtriple=x86_64. It was incompatible on i686 and Windows x64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 09:37:54 +00:00
Craig Topper
1d90bbba14 Remove MMX shift intrinsic handling code that also exists in SelectionDAGBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 08:08:30 +00:00
Craig Topper
43e4c62c43 Commit test change for r162658.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162660 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 07:55:50 +00:00
Alexey Samsonov
07071c1c75 [DebugInfo] fixup for r162657: update CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 07:24:43 +00:00
Craig Topper
58bfb27c4b Don't allow vextractf128 to be folded with unaligned stores. We don't fold unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 07:19:59 +00:00
Alexey Samsonov
eceb5b9977 Add basic support for .debug_ranges section to LLVM's DebugInfo library.
This section (introduced in DWARF-3) is used to define instruction address
ranges for functions that are not contiguous and can't be described
by low_pc/high_pc attributes (this is the usual case for inlined subroutines).
The patch is the first step to support fetching complete inlining info from DWARF.

Reviewed by Benjamin Kramer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 07:17:47 +00:00
Craig Topper
903090c55e Fold some patterns into instruction definitons so tablegen can infer flags removing the need for an explicit 'neverHasSideEffects = 1'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 07:04:50 +00:00
Anitha Boyapati
0aa63fcbcb FMA3 tests on bdver2 target for changes made in rev 162012. Also made
corresponding changes to existing tests for darwin triple to ensure that
same pattern is tested for bdver2 target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 06:59:01 +00:00
Craig Topper
3a1683f88f Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 06:08:57 +00:00
Craig Topper
e10fa862f8 Make sure that FMA3 is favored even when FMA4 is also enabled. Test case for r162454.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 03:38:15 +00:00
Rafael Espindola
a16c2e3493 Pass -lLTO after gold-plugin.o so that it gets used in systems that default to
--as-needed.
Patch by Felix Geyer. Fixes pr13262.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27 03:03:07 +00:00
Craig Topper
e3677a66fa Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Richard Smith
1144af3c9b Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 23:29:28 +00:00
Jakob Stoklund Olesen
cac59d8ae8 Add missing mayLoad flags to a large class of AVX *_Int instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 23:29:07 +00:00
Jakob Stoklund Olesen
36ff8f25c5 Missed tLEApcrelJT.
ARMConstantIslandPass expects this instruction to stay in the same basic
block as the jump table branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 22:46:55 +00:00
Jakob Stoklund Olesen
4ad27eda29 Infer instruction properties from single-instruction patterns.
Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.

This causes a lot of instruction flags to change.

- Many instructions no longer have the UnmodeledSideEffects flag because
  their flags are now inferred from a pattern.

- Instructions with intrinsics will get a mayStore flag if they already
  have UnmodeledSideEffects and a mayLoad flag if they already have
  mayStore. This is because intrinsics properties are linear.

- Instructions with atomic_load patterns get a mayStore flag because
  atomic loads can't be reordered. The correct workaround is to create
  pseudo-instructions instead of using normal loads. PR13693.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 22:46:53 +00:00
Jakob Stoklund Olesen
7778ee1ed9 Explicitly mark LEApcrel pseudos with hasSideEffects.
It's not clear that they should be marked as such, but tbb formation
fails if t2LEApcrelJT is hoisted of of a loop.

This doesn't change the flags on these instructions,
UnmodeledSideEffects was already inferred from the missing pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 21:44:11 +00:00
Jakob Stoklund Olesen
aaaecfce70 Stop inferring isVariadic from instruction patterns.
Instructions are now only marked as variadic if they use variable_ops in
their ins list.

A variadic SDNode is typically used for call nodes that have the call
arguments as operands.

A variadic MachineInstr can actually encode a variable number of
operands, for example ARM's stm/ldm instructions. A call instruction
does not have to be variadic. The call argument registers are added as
implicit operands.

This change remove the MCID::Variadic flags from most call and return
instructions, allowing us to better verify their operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 21:08:09 +00:00
Jakob Stoklund Olesen
0745b649ed Fix call instruction operands in ARMFastISel.
The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.

The argument registers should be added as implicit uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 20:52:46 +00:00
Jakob Stoklund Olesen
9511a460d8 Mark X86::RET and RETI instructions as variadic.
There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 20:52:44 +00:00
Jakob Stoklund Olesen
baa74e4b35 Avoid including explicit uses when counting SDNode imp-uses.
It is legal to have a register node as an explicit operand, it shouldn't
be counted as an implicit use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 20:52:42 +00:00
Akira Hatanaka
16865d0612 Disable Mips' delay slot filler when optimization level is O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 20:40:15 +00:00
Akira Hatanaka
45d8dbc92d In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its
second operand is MipsISD::GPRel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 20:21:49 +00:00
Manman Ren
6adeb67b33 Forgot to check in ProfileDataTypes.h in r162576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 18:40:00 +00:00
Manman Ren
cd62c28723 Profile: move a single enum out of ProfileInfoTypes.h into a new
ProfileDataTypes.h header.

With this patch the old and new profiling code can exist side-by-side. The new
profiling code will be submitted soon and it only supports insert-edge-profiling
for now and will not depend on ProfileInfo.

Patch by Alastair Murray.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 18:31:44 +00:00
Manman Ren
1a710fdde1 BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle
the case of multiple edges from one block to another.

A simple example is a switch statement with multiple values to the same
destination. The definition of an edge is modified from a pair of blocks to
a pair of PredBlock and an index into the successors.

Also set the weight correctly when building SelectionDAG from LLVM IR,
especially when converting a Switch.
IntegersSubsetMapping is updated to calculate the weight for each cluster.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 18:14:27 +00:00
Jakob Stoklund Olesen
91f8dc9bae Verify explicit instruction properties when they can be inferred.
It is now allowed to explicitly set hasSideEffects, mayStore, and
mayLoad on instructions with patterns.

Verify that the patterns are consistent with the explicit flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 17:08:41 +00:00
Kostya Serebryany
b5b86d263a [asan/tsan] rename FunctionBlackList* to BlackList* as this class is not limited to functions any more
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 16:44:47 +00:00
Kostya Serebryany
2c5380666a [asan/tsan] extend the functionality of FunctionBlackList to globals and modules. Patch by Reid Watson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 16:40:11 +00:00
Roman Divacky
9fb8b49380 Lower constant pools and jump tables via TOC on PPC64/SVR4.
In collaboration with Adhemerval Zanella.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 16:26:02 +00:00
Benjamin Kramer
bd7684c94c GVN: Fix quadratic runtime on the number of switch cases.
No intended behavior change.  This was introduced in r162023.  With the fixed
algorithm a Release build of ARMInstPrinter.cpp goes from 16s to 10s on a
2011 MBP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162559 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 15:06:28 +00:00
Jakob Stoklund Olesen
4d320db5d1 Fix load/store SDNode flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 14:43:30 +00:00
Jakob Stoklund Olesen
ea47628cba Add missing SDNPSideEffect flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 14:43:27 +00:00
Jakob Stoklund Olesen
3d2a2d1217 Remove more mayLoad workarounds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 14:43:22 +00:00
Chandler Carruth
be06428ba3 Try to appease MSVC even more elaborately in the alignment hacking space.
MSVC doesn't support passing by-value parameters with alignment of
16-bytes or higher apparantly. What is deeply confusing is that it seems
to *sometimes* (but not always) apply this to any type whose alignment
is set using __declspec(align(...)). This caused lots of errors when we switch
SmallVector over to use the automatically aligned character array
utilities as they used __declspec(align(...)) heavily.

As a pretty horrible but effective work-around, we instead cherry pick
the smallest alignment sizes with specific types that happen to have the
correct alignment, and then fall back to the attribute solution past
them. This should resolve the MSVC build errors folks have been hitting.
Sorry for that. In good news, it will do this without introducing other
UB I hope. =]

Thanks to Timur Iskhodzhanov for helping me test this!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162549 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 09:53:43 +00:00
Craig Topper
0e292376d0 Custom lower FMA intrinsics to target specific nodes and remove the patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162534 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 04:03:22 +00:00
Eric Christopher
873cf0a0d7 Use DW_FORM_flag_present to save space in debug information if we're
not in darwin gdb compat mode.

Fixes rdar://10975088

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 01:14:27 +00:00
Eric Christopher
3887a902a1 Add support for some missing DW_FORM_*.
TODO: Fix code duplication and coding style.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 01:14:23 +00:00
Eric Christopher
08cdb6e6b2 Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 01:14:21 +00:00
Richard Smith
aaf217953b Fix undefined behavior (negation of INT_MIN) in ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 00:35:46 +00:00
Richard Smith
9e085a8637 Fix floating-point divide by zero, in a case where the value was not going to be used anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 00:31:45 +00:00
Jakob Stoklund Olesen
6211386799 Remove some spurious mayLoad = 0 flags.
They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162517 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 00:31:20 +00:00
Jakob Stoklund Olesen
912519a72e Heed guessInstructionProperties, and stop warning on redundant flags.
Emit TableGen errors if guessInstructionProperties is 0 and
instruction properties can't be inferred from patterns.

Allow explicit instruction properties even when they can be inferred.

This patch doesn't change the TableGen output. Redundant properties
are not yet verified because the tree has errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 00:31:16 +00:00
Jakob Stoklund Olesen
02c63803e5 Add missing SDNP properties on the flushw node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162515 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 00:31:13 +00:00
Jakob Stoklund Olesen
cfe8a9695b X86MemBarrier has unmodeled side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162514 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 00:31:10 +00:00
Richard Smith
b080e2fb1c Fix undefined behavior (signed integer overflow) when Clang parses a hexfloat with an enormous exponent. Caught by an existing unit test + -ftrapv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 00:01:19 +00:00
Eric Christopher
5d04a3ad0e Formatting cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 23:26:57 +00:00