Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.
The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.
This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.
The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
handles dead implicit results more aggressively. More
to come, I think this is now just a data entry problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99486 91177308-0d34-0410-b5e6-96231b3b80d8
addl $12, %esp
popl %esi
popl %edi
popl %ebx
popl %ebp
jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL
The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.
The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99455 91177308-0d34-0410-b5e6-96231b3b80d8
--- Reverse-merging r99440 into '.':
U test/MC/AsmParser/X86/x86_32-bit_cat.s
U test/MC/AsmParser/X86/x86_32-encoding.s
U include/llvm/IntrinsicsX86.td
U include/llvm/CodeGen/SelectionDAGNodes.h
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99450 91177308-0d34-0410-b5e6-96231b3b80d8
not get an "Unknown immediate size" assert failure when used. All instructions
of this form have an 8-bit immediate. Also added a test case of an example
instruction that is of this form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
ISD node. The only change in the generated isel code are comments
like:
< // Src: (X86dec_flag:i16 GR16:i16:$src)
---
> // Src: (X86dec_flag:i16:i32 GR16:i16:$src)
because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case. Wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99369 91177308-0d34-0410-b5e6-96231b3b80d8
This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99345 91177308-0d34-0410-b5e6-96231b3b80d8
caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99032 91177308-0d34-0410-b5e6-96231b3b80d8
override prefix and only the r/m16 forms should have had that. Also for variant
one, the AT&T syntax, added suffixes to all forms. Also added the missing
64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
- MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98955 91177308-0d34-0410-b5e6-96231b3b80d8
dag isel gen instead of instruction properties. This
allows the oh-so-useful behavior of matching a variadic
non-root node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
can't match or just have no testcases. Will remove after
confirmation from dan that they really are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98930 91177308-0d34-0410-b5e6-96231b3b80d8
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
temporary workaround for matching inc/dec on x86_64 to the correct instruction.
- This hack will eventually be replaced with a robust mechanism for handling
matching instructions based on the available target features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98858 91177308-0d34-0410-b5e6-96231b3b80d8
