Commit Graph

364 Commits

Author SHA1 Message Date
Devang Patel
9194c6716b If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example,
DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134620 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 17:45:33 +00:00
Jakob Stoklund Olesen
d519de0827 Include a source location when complaining about bad inline assembly.
Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134307 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 03:53:34 +00:00
Cameron Zwarich
c20fb63ebd Take a stab at fixing the llvm-x86_64-linux-checks failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 23:45:21 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 19:10:37 +00:00
Jakob Stoklund Olesen
f792fa90f1 Distinguish early clobber output operands from clobbered registers.
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

  asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

  asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 04:08:33 +00:00
Jakob Stoklund Olesen
7a2ecd3f99 Decode and pretty print inline asm operand descriptors.
The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:

  INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 04:08:29 +00:00
Devang Patel
8594d429e0 Handle debug info for i128 constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 20:46:11 +00:00
Evan Cheng
cbc988be22 Re-commit 131172 with fix. MachineInstr identity checks should check dead
markers. In some cases a register def is dead on one path, but not on
another.

This is passing Clang self-hosting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131214 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-12 00:56:58 +00:00
Jakob Stoklund Olesen
cf724f0786 Remove an assertion to fix PR9872.
It can happen that a live debug variable is the last use of a sub-register, and
the register allocator will pick a larger register class for the virtual
register.  If the allocated register doesn't support the sub-register index,
just use %noreg for the debug variables instead of asserting.

In PR9872, a debug variable ends up in the sub_8bit_hi part of a GR32_ABCD
register. The register is split and one part is inflated to GR32 and assigned
%ESI because there are no more normal uses of sub_8bit_hi.

Since %ESI doesn't have that sub-register, substPhysReg asserted. Now it will
simply insert a %noreg instead, and the debug variable will be marked
unavailable in that range.

We don't currently have a way of saying: !"value" is in bits 8-15 of %ESI, I
don't know if DWARF even supports that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-08 19:21:08 +00:00
Bill Wendling
d65ba721cc Print out the 'nontemporal' info on a store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 23:45:22 +00:00
Jakob Stoklund Olesen
b793bc1cca Ensure all defs referring to a virtual register are marked dead by addRegisterDead().
There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 16:53:50 +00:00
Anton Korobeynikov
6dd97471c4 Add FrameSetup MI flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:43:04 +00:00
Jakob Stoklund Olesen
c9df025e33 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10 02:58:51 +00:00
Jakob Stoklund Olesen
4314268128 Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.
Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09 03:05:53 +00:00
Evan Cheng
c36b7069b4 Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07 23:50:32 +00:00
Evan Cheng
30a343aeed DBG_VALUE does not have any side effects; it also makes no sense to mark it cheap as a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07 21:08:26 +00:00
Evan Cheng
c8f46c45a0 Unbreak build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 21:49:09 +00:00
Dan Gohman
f96e4bd2a3 Make CodeGen TBAA-aware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 00:31:05 +00:00
Jakob Stoklund Olesen
2594746045 Shrink MachineOperand from 40 to 32 bytes on 64-bit hosts.
Pull an unsigned out of the Contents union such that it has the same size as two
pointers and no padding.

Arrange members such that the Contents union and all pointers can be 8-byte
aligned without padding.

This speeds up code generation by 0.8% on a 64-bit host. 32-bit hosts should be
unaffected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 20:56:32 +00:00
Chris Lattner
fc448ff89b convert a couple more places to use the new getStore()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:51:21 +00:00
Chris Lattner
1daa6f479d add some accessors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:43:24 +00:00
Chris Lattner
e8639036b1 it's more elegant to put the "getConstantPool" and
"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 06:22:23 +00:00
Chris Lattner
40a858f6e7 add some helpful accessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114400 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 05:39:30 +00:00
Chris Lattner
da39c39644 start pushing MachinePointerInfo out through the MachineMemOperand interface
to the MachineFunction construction methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 04:32:08 +00:00
Chris Lattner
e8e2e80f40 refactor the Value*/offset pair from MachineMemOperand out to a new
MachinePointerInfo struct, no functionality change.

This also adds an assert to MachineMemOperand::MachineMemOperand
that verifies that the Value* is either null or is an IR pointer type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 04:23:39 +00:00
Oscar Fuentes
ee56c42168 Prefix next' iterator operation with llvm::'.
Fixes potential ambiguity problems on VS 2010.

Patch by nobled!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02 06:00:15 +00:00
Jakob Stoklund Olesen
a0c5bf19bf Print out the regclass of any virtual registers used by a machine instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 18:35:46 +00:00
Jakob Stoklund Olesen
b1e11455d1 Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107602 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-04 23:24:23 +00:00
Dale Johannesen
f1e309eb48 Propagate the AlignStack bit in InlineAsm's to the
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not.  gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks.  There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it.  PR 5125.  Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now.  I'm not making it any
worse.  If anyone is inspired I think you can find all
the right places from this patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 20:16:09 +00:00
Devang Patel
da0e89f4c4 Print InlinedAt location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107208 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 21:51:32 +00:00
Dan Gohman
db4971259c Teach regular and fast isel to set dead flags on unused implicit defs
on calls and similar instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:28:01 +00:00
Jakob Stoklund Olesen
9edf7deb37 Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

  %reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

  %reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 22:47:25 +00:00
Jakob Stoklund Olesen
a5135f60dd Properly compose subregister indices when coalescing.
The comment about ordering of subreg indices is no longer true.
This exposed a bug in the new substVirtReg method that is also fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-01 22:39:25 +00:00
Jakob Stoklund Olesen
2da5337024 Add a TargetRegisterInfo::composeSubRegIndices hook with a default
implementation that is correct for most targets. Tablegen will override where
needed.

Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 18:18:53 +00:00
Jakob Stoklund Olesen
1fc8e759a7 Print symbolic SubRegIndex names on machine operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:38 +00:00
Evan Cheng
1015ba7018 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
18b2c9d3bf Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 20:02:01 +00:00
Jakob Stoklund Olesen
19f5f71bba Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
This reverts r104322. I think it was causing miscompilations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
00c53caa33 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
This correctly handles partial redefines and undef uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
63e6a488cb If the first definition of a virtual register is a partial redef, add an
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:32:16 +00:00
Jakob Stoklund Olesen
7ebc4d63db Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:36:22 +00:00
Dan Gohman
e6cd757e68 Teach MachineLICM and MachineSink how to clear kill flags conservatively
when they move instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 20:34:42 +00:00
Evan Cheng
59b3655564 Pretty print DBG_VALUE machine instructions.
Before:
DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707
Now:
DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 20:03:13 +00:00
Bob Wilson
1793ab9e70 Use getNumImplicitDefs() and getNumImplicitUses().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 04:46:43 +00:00
Bob Wilson
0855cadb00 Fix up some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 04:34:03 +00:00
Evan Cheng
a57fabe815 Coalescer should not delete copy instructions whose defs are partially dead. e.g.
%RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 20:02:37 +00:00
Chris Lattner
24ad3ed71f fix a latent bug my inline asm stuff exposed:
MachineOperand::isIdenticalTo wasn't handling metadata operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100636 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:03:19 +00:00
Chris Lattner
a4f2bb08de stop using DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 20:17:23 +00:00
Chris Lattner
de4845c163 Switch the code generator (except the JIT) onto the new DebugLoc
representation.  This eliminates the 'DILocation' MDNodes for 
file/line/col tuples from -O0 -g codegen.

This remove the old DebugLoc class, making it a typedef for DebugLoc,
I'll rename NewDebugLoc next.

I didn't update the JIT to use the new apis, so it will continue to
work, but be as slow as before.  Someone should eventually do this
or, better yet, rip out the JIT debug info stuff and build the JIT
on top of MC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 19:42:39 +00:00
Chris Lattner
72aaa3c798 add support for MCSymbols as operands to MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 08:14:18 +00:00