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Commit Graph

2345 Commits

Author SHA1 Message Date
Nadav Rotem
4332bdcb5f Make LegalizeKind public so that we can use it outside of TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24 20:59:17 +00:00
Nadav Rotem
2704834661 Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24 17:22:41 +00:00
Nadav Rotem
cbd9a19b5d Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18 23:22:48 +00:00
Bob Wilson
3b9a911efc Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang.  I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.

This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18 05:43:52 +00:00
Stepan Dyatkovskiy
b52ba9f8a8 Issue:
Stack is formed improperly for long structures passed as byval arguments for
EABI mode.

If we took AAPCS reference, we can found the next statements:

A: "If the argument requires double-word alignment (8-byte), the NCRN (Next
Core Register Number) is rounded up to the next even register number." (5.5
Parameter Passing, Stage C, C.3).

B: "The alignment of an aggregate shall be the alignment of its most-aligned
component." (4.3 Composite Types, 4.3.1 Aggregates).

So if we have structure with doubles (9 double fields) and 3 Core unused
registers (r1, r2, r3): caller should use r2 and r3 registers only.
Currently r1,r2,r3 set is used, but it is invalid.

Callee VA routine should also use r2 and r3 regs only. All is ok here. This
behaviour is guessed by rounding up SP address with ADD+BFC operations.

Fix:
Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and
8 byte alignment, we waste odd registers then.

P.S.:
I also improved LDRB_POST_IMM regression test. Since ldrb instruction will
not generated by current regression test after this patch. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166018 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 07:16:47 +00:00
Micah Villmow
2c39b15073 Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 16:24:29 +00:00
Nick Lewycky
f117f93f6e Shuffle the virtual destructor down to the base. This should actually pacify
-Wnon-virtual-dtor for real.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12 04:28:25 +00:00
Nick Lewycky
863ff7c903 Give this class full of virtual functions a virtual destructor. Classes love
virtual destructors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165786 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12 04:13:25 +00:00
Micah Villmow
fb384d61c7 Revert 165732 for further review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 21:27:41 +00:00
Micah Villmow
f3840d2c16 Add in the first iteration of support for llvm/clang/lldb to allow variable per address space pointer sizes to be optimized correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11 17:21:41 +00:00
Nadav Rotem
e3d0e86919 Add a new interface to allow IR-level passes to access codegen-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 22:04:55 +00:00
Stepan Dyatkovskiy
661afe75e8 Issue description:
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack
objects and byval parameters. So loading byval parameters from stack may be
inserted *before* it will be stored, since these operations are treated as
independent.

Fix:
Currently ARMTargetLowering::LowerFormalArguments saves byval registers with
FixedStack MachinePointerInfo. To fix the problem we need to store byval
registers with MachinePointerInfo referenced to first the "byval" parameter.

Also commit adds two new fields to the InputArg structure: Function's argument
index and InputArg's part offset in bytes relative to the start position of
Function's argument. E.g.: If function's argument is 128 bit width and it was
splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index,
but different offset values. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 11:37:36 +00:00
Andrew Trick
412cd2f813 misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 05:43:09 +00:00
Bill Wendling
3e2d76c946 Use the attribute enums to query if a parameter has an attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 21:38:14 +00:00
Micah Villmow
7d66146868 Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size.
The next step is to update the optimizers to allow them to optimize the different address spaces with this information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 16:06:12 +00:00
Nadav Rotem
03753aa759 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165475 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 01:56:07 +00:00
Nadav Rotem
ad6aedc7d9 Refactor the AddrMode class out of TLI to its own header file.
This class is used by LSR and a number of places in the codegen.
This is the first step in de-coupling LSR from TLI, and creating
a new interface in between them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 23:06:34 +00:00
Andrew Trick
39817f9d39 misched: remove the unused getSpecialAddressLatency hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 18:54:00 +00:00
Micah Villmow
3574eca1b0 Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 16:38:25 +00:00
Chad Rosier
f420eeccbe Remove extraneous semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165319 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05 17:15:19 +00:00
Micah Villmow
bf07a512f2 Implement TargetData with the DataLayout class, this will allow LLVM projects to transition to DataLayout without loosing functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05 17:02:14 +00:00
Preston Gurd
8d662b59f0 This patch corrects commit 165126 by using an integer bit width instead of
a pointer to a type, in order to remove the uses of getGlobalContext().

Patch by Tyler Nowicki.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 21:33:40 +00:00
Bill Wendling
5d0061e025 Use attribute query methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165210 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04 07:08:30 +00:00
Andrew Trick
13745262a8 Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 23:06:32 +00:00
Benjamin Kramer
90012586f7 TargetData: s/uint32_t/unsigned/ per Kuba's request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01 11:56:16 +00:00
Benjamin Kramer
01e872af25 Shrink TargetAlignElem a bit, we do a lot of searches on them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29 19:57:14 +00:00
Sebastian Pop
1a37d7e807 TargetLowering interface to set/get minimum block entries for jump tables.
Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.

    getMinimumJumpTableEntries() defaults to 4.
    setMinimumJumpTableEntries() allows target configuration.

    This patch changes the default for the Hexagon architecture to 5
    as it improves performance on some benchmarks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25 20:35:36 +00:00
Andrew Trick
9264988311 Machine Model (-schedmodel only). Added SchedAliases.
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22 02:24:21 +00:00
Andrew Trick
34301ceca8 TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164098 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 04:03:34 +00:00
Andrew Trick
ee290ba35a TableGen subtarget emitter. Remove unnecessary header dependence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:32:57 +00:00
Andrew Trick
e127dfd0b1 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:18:56 +00:00
Andrew Trick
e1b5328717 Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:00:42 +00:00
NAKAMURA Takumi
89a4058da1 llvm/Target/TargetSubtargetInfo.h: Fix case in #include, s#llvm/Codegen/#llvm/CodeGen#.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164070 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:34:56 +00:00
Andrew Trick
12886db4a7 TargetSchedModel API. Implement latency lookup, disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164065 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:19:08 +00:00
Andrew Trick
021ba269b2 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:58 +00:00
Andrew Trick
db7afac457 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:55 +00:00
Craig Topper
001d3dc976 Mark unimplemented copy constructors and copy assignment operators as LLVM_DELETED_FUNCTION.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164016 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 06:59:23 +00:00
Andrew Trick
0303d92b73 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163932 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 20:26:39 +00:00
Micah Villmow
d15e657690 Add in comments that explain what the indexing and the size of the arrays is about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 15:36:50 +00:00
Andrew Trick
a2ed0e8e8b misched: Generic tablegen classes for the new machine model.
This is mostly documentation for the new machine model. It is designed
to be flexible, easy to incrementally refine for a subtarget, and
provide all the information that MachineScheduler will need.

If all goes well, I will follow up with an example of the new model in
use for ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 06:18:55 +00:00
Andrew Trick
1008f8c789 comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 06:18:52 +00:00
Andrew Trick
8fa5319504 comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 06:18:50 +00:00
Micah Villmow
af40a5be77 The current implementation does not allow more than 32 types to be properly handled with target lowering. This doubles the size to 64bit types and easily allows extension to more types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 15:24:43 +00:00
Owen Anderson
83c0eefa3b Improve tblgen code cleanliness: create an unknown_class, from which the unknown def inherits. Make tblgen check for that class, rather than checking for the def itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 23:47:08 +00:00
Jakob Stoklund Olesen
a6035773d8 Add TRI::getSubRegIndexLaneMask().
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.

The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.

Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 16:34:08 +00:00
Jakob Stoklund Olesen
59f45e4610 Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.
Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 16:34:02 +00:00
Tom Stellard
6d3d765653 Tablegen: Add OperandWithDefaultOps Operand type
This Operand type takes a default argument, and is initialized to
this value if it does not appear in a patter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 14:15:52 +00:00
Nadav Rotem
c05d30601c Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 09:17:37 +00:00
Preston Gurd
2e2efd9600 Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder,  or both.

Patch by Tyler Nowicki!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 18:22:17 +00:00
Nadav Rotem
9f40cb32ac Not all targets have efficient ISel code generation for select instructions.
For example, the ARM target does not have efficient ISel handling for vector
selects with scalar conditions. This patch adds a TLI hook which allows the
different targets to report which selects are supported well and which selects
should be converted to CF duting codegen prepare.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02 12:10:19 +00:00