6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-23 01:30:19 +00:00
Code Issues Projects Releases Wiki Activity
75,836 Commits 39 Branches 0 Tags 277 MiB
457d53d9ce
Commit Graph

3075 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
457d53d9ce Revert the wrong part of r139528, and fix testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 21:24:07 +00:00
Bruno Cardoso Lopes
8e03a821f9 Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't. 
However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-12 19:30:40 +00:00
Eli Friedman
cfeb55cdbc Really un-XFAIL the testcase, like I said I would in r139458. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 02:02:27 +00:00
Richard Trieu
2db8628085 Fixed an assert from: 
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 01:26:21 +00:00
Nadav Rotem
8ffad56f8e Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:29:17 +00:00
Bruno Cardoso Lopes
7ec8fb8830 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes
7cf79a88c8 Reapply testcase from r139309! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 21:05:43 +00:00
Bruno Cardoso Lopes
caa60f15e4 Remove this crashing test, until I figure out what's going wrong here 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139309 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes
814c6ced85 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. 
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:05:02 +00:00
Nadav Rotem
cbdd2d10ba add a testcase for the previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 08:31:31 +00:00
Eli Friedman
d5ccb0558f Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()). 
This isn't exactly ideal, but it is good enough for the moment.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 18:48:32 +00:00
Duncan Sands
68b859f757 Another forgotten trampoline testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139230 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 10:05:14 +00:00
Devang Patel
541a81cc2b While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139208 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 00:07:58 +00:00
Jakob Stoklund Olesen
5047d76575 Pseudo CMOV instructions don't clobber EFLAGS. 
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 23:52:55 +00:00
Eli Friedman
4136d23c48 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 22:33:24 +00:00
Duncan Sands
147272b8a7 Darwin wants ctors/dtors to be ordered the other way round to linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:07:19 +00:00
Benjamin Kramer
d4f27d7daa This test depends on cmov being available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 18:40:01 +00:00
Bruno Cardoso Lopes
a39ccdb9d4 Fix vbroadcast matching logic to early unmatch if the node doesn't have 
only one use. Fix PR10825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138951 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 18:15:06 +00:00
Andrew Trick
340d78f4e7 PreRA scheduler should avoid cloning compares. 
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 00:54:31 +00:00
Bill Wendling
78ae1f7947 Remove old declare statements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138905 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:41:20 +00:00
Bill Wendling
6b94b67319 Update more tests to the new EH scheme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138904 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:40:15 +00:00
Bill Wendling
935903191f Update more tests to the new EH scheme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 21:39:05 +00:00
David Greene
d92e2e4f88 Compress Repeated Byte Output 
Emit a repeated sequence of bytes using .zero.  This saves an enormous
amount of asm file space for certain programs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 17:30:56 +00:00
Benjamin Kramer
31d27ce568 This test requires sse, otherwise x87 ops will block tailcall optimization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138859 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 16:49:05 +00:00
Bruno Cardoso Lopes
57d6a5e491 - Move all MOVSS and MOVSD patterns close to their definitions 
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138851 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 03:04:20 +00:00
Evan Cheng
0899f5c62d Fix (movhps load) lowering / pattern to match more cases. rdar://10050549 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138848 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 02:05:24 +00:00
Benjamin Kramer
8f00ffce50 Fix test typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 00:02:59 +00:00
Rafael Espindola
6cac2025da Add a triple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138831 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 21:19:37 +00:00
Rafael Espindola
b0bf8935ee Some test code to check if correct code is being generated. 
Patch by Sanjoy Das.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138820 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 19:51:29 +00:00
Eli Friedman
f3704769bb Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138768 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 21:15:46 +00:00
Duncan Sands
fd9c4f76f4 Fix PR5329: pay attention to constructor/destructor priority 
when outputting them.  With this, the entire LLVM testsuite
passes when built with dragonegg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-28 13:17:22 +00:00
Bill Wendling
234e43a888 Update to new EH scheme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 04:53:41 +00:00
Bill Wendling
f2cf25b212 Cannot have an llvm.eh.exception call in a non-landing pad block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138698 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 04:53:28 +00:00
Eli Friedman
43f51aeca8 Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:21:21 +00:00
Bruno Cardoso Lopes
6292eceea0 Add support for AVX 256-bit version of MOVDDUP! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 21:40:37 +00:00
Bruno Cardoso Lopes
07b7f672a0 Add support for 256-bit versions of VSHUFPD and VSHUFPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 02:58:26 +00:00
Eli Friedman
f8f90f0174 Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:33:28 +00:00
Eli Friedman
bbc87a3a9a Basic tests for atomic load and store on x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:16:59 +00:00
Craig Topper
13894fa135 Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 06:14:18 +00:00
Bruno Cardoso Lopes
d8b7dd5252 Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit 
permutations. Also tidy up some patterns and make them close to their
instruction definition!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138392 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 22:06:37 +00:00
Nick Lewycky
726ebd6ff3 PerformSubCombine to work on integers larger than i128. Fixes a crasher. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 19:01:24 +00:00
Craig Topper
a534780da0 Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 04:36:33 +00:00
Bruno Cardoso Lopes
3bde6fe0df Introduce a pass to insert vzeroupper instructions to avoid AVX to 
SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-23 01:14:17 +00:00
Bruno Cardoso Lopes
2ac8111159 Add support for breaking 256-bit int VETCC into two 128-bit ones, 
avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138271 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-22 20:31:04 +00:00
Jakob Stoklund Olesen
7c6da77810 Add test case for r138018. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138033 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-19 04:30:24 +00:00
Ivan Krasin
74af88a666 FastISel: avoid function calls between the materialization of the constant and its use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137993 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:06:10 +00:00
Bruno Cardoso Lopes
24b90e2287 Cleanup vector logical ops in AVX and add use int versions for simple 
v2i64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137919 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 02:11:34 +00:00
Bruno Cardoso Lopes
0dd80b0d69 Fix PR10688. Add support for spliting 256-bit vector shifts when the 
shift amount is variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:12:20 +00:00
Bruno Cardoso Lopes
0e6d230abd Introduce matching patterns for vbroadcast AVX instruction. The idea is to 
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 02:29:19 +00:00