Commit Graph

39 Commits

Author SHA1 Message Date
Dan Gohman
475871a144 Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-27 21:46:04 +00:00
Duncan Sands
126d90770b Rather than having a different custom legalization
hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes.  No change if the
new LegalizeTypes infrastructure is not turned on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53137 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-04 11:47:58 +00:00
Duncan Sands
83ec4b6711 Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06 12:08:01 +00:00
Dan Gohman
1f13c686df Fix the SVOffset values for loads and stores produced by
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 17:15:20 +00:00
Dan Gohman
29e4bdbf27 Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49666 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-14 17:55:48 +00:00
Dan Gohman
707e018423 Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00
Dan Gohman
977a76fbb6 Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 22:28:48 +00:00
Dan Gohman
fd29e0eb06 Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 00:35:47 +00:00
Nate Begeman
c451ac0a42 This method should be virtual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46723 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-04 23:04:24 +00:00
Evan Cheng
ff9b373e8f Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-30 18:18:23 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Chris Lattner
f1b1c5ed1a implement a trivial readme entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44380 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-27 22:36:16 +00:00
Chris Lattner
27a6c7380f Several changes:
1) Change the interface to TargetLowering::ExpandOperationResult to 
   take and return entire NODES that need a result expanded, not just
   the value.  This allows us to handle things like READCYCLECOUNTER,
   which returns two values.
2) Implement (extremely limited) support in LegalizeDAG::ExpandOp for MERGE_VALUES.
3) Reimplement custom lowering in LegalizeDAGTypes in terms of the new
   ExpandOperationResult.  This makes the result simpler and fully 
   general.
4) Implement (fully general) expand support for MERGE_VALUES in LegalizeDAGTypes.
5) Implement ExpandOperationResult support for ARM f64->i64 bitconvert and ARM
   i64 shifts, allowing them to work with LegalizeDAGTypes.
6) Implement ExpandOperationResult support for X86 READCYCLECOUNTER and FP_TO_SINT,
   allowing them to work with LegalizeDAGTypes.

LegalizeDAGTypes now passes several more X86 codegen tests when enabled and when
type legalization in LegalizeDAG is ifdef'd out.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44300 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-24 07:07:01 +00:00
Rafael Espindola
f1ba1cad38 Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-05 23:12:20 +00:00
Rafael Espindola
e0703c84dd Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold
and by restructuring the X86 version.

New I just have to move this to a common place :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-31 14:39:58 +00:00
Evan Cheng
4102eb57bb Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-22 22:11:27 +00:00
Rafael Espindola
7b73a5d6de split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43176 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-19 14:35:17 +00:00
Dan Gohman
525178cdbf Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-08 18:33:35 +00:00
Duncan Sands
f7331b3dd7 Fold the adjust_trampoline intrinsic into
init_trampoline.  There is now only one
trampoline intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-11 14:10:23 +00:00
Dan Gohman
61e729e2e9 More explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 21:21:54 +00:00
Duncan Sands
36397f5034 Support for trampolines, except for X86 codegen which is
still under discussion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-27 12:58:54 +00:00
Dan Gohman
ea859be53c Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 14:59:07 +00:00
Evan Cheng
277f0741c5 Allow predicated immediate ARM to ARM calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37659 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 21:05:09 +00:00
Dale Johannesen
8dd86c14d4 More effective breakdown of memcpy into repeated load/store. These are now
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37179 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-17 21:31:21 +00:00
Lauro Ramos Venancio
64f4fa5e0e ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36506 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 13:54:47 +00:00
Lauro Ramos Venancio
0ae4a3357a Implement PIC for arm-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36324 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-22 00:04:12 +00:00
Chris Lattner
37caf8c68e remove dead target hooks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35846 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 23:33:39 +00:00
Chris Lattner
b445d0cbb9 remove some dead target hooks, subsumed by isLegalAddressingMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 22:27:04 +00:00
Lauro Ramos Venancio
9996663fc6 - Divides the comparisons in two types: comparisons that only use N and Z
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-02 01:30:03 +00:00
Chris Lattner
c9addb7488 implement the new addressing mode description hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35521 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30 23:15:24 +00:00
Evan Cheng
caaf69107e Remove isLegalAddressImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 01:53:55 +00:00
Chris Lattner
4234f57fa0 switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-25 02:14:49 +00:00
Dale Johannesen
fa4bce2b76 repair x86 performance, dejagnu problems from previous change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-21 21:51:52 +00:00
Dale Johannesen
8e59e163db do not share old induction variables when this would result in invalid
instructions (that would have to be split later)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35227 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 21:54:54 +00:00
Dale Johannesen
80dae195c7 fix obvious comment bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35196 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 00:30:56 +00:00
Evan Cheng
2770747216 Added isLegalAddressExpression(). Only allows X +/- C for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35122 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-16 08:43:56 +00:00
Evan Cheng
b01fad6d19 Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35075 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-12 23:30:29 +00:00
Evan Cheng
c60e76d139 - Fix codegen for pc relative constant (e.g. JT) in thumb mode:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33664 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-30 20:37:08 +00:00
Evan Cheng
a8e2989ece ARM backend contribution from Apple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19 07:51:42 +00:00