Evan Cheng
18fb1d35db
Add Mode64Bit feature and sink it down to MC layer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 21:06:52 +00:00
Bill Wendling
4ae970b393
Move a function out-of-line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134640 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 21:05:13 +00:00
Akira Hatanaka
03236be44a
Rather than having printMemOperand change the way memory operands are printed
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based on a modifier, split it into two functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:54:20 +00:00
Akira Hatanaka
17a2f8e551
Define class MipsMCInstLower.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:24:54 +00:00
Akira Hatanaka
aa08ea0530
Change visibility of MipsAsmPrinter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 20:10:52 +00:00
Akira Hatanaka
2091a0d8d2
Define class MipsMCSymbolRefExpr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134629 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 19:27:22 +00:00
Akira Hatanaka
4d1abf1a38
Simplify MipsRegisterInfo::eliminateFrameIndex.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134628 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 19:13:09 +00:00
Evan Cheng
4761a8d654
Rewrite comment in English.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 19:09:06 +00:00
Evan Cheng
963b03c1a9
Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 19:05:12 +00:00
Akira Hatanaka
d3ac47f805
Reverse order of operands of address operand mem so that the base operand comes
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before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 18:57:00 +00:00
Akira Hatanaka
e280519ba6
Add missing return statement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134622 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 18:27:36 +00:00
Oscar Fuentes
a8504111f6
Update CMake library dependencies
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134616 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 16:33:00 +00:00
Douglas Gregor
7f358da70f
Fix CMake build
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134614 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 15:59:22 +00:00
Cameron Zwarich
375db7f39a
The VMLA instruction and its friends are not actually fused; they're plain old
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multiply-accumulate instructions with separate rounding steps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134609 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 08:28:52 +00:00
Evan Cheng
db068738e8
Sink feature IsThumb into MC layer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 08:26:46 +00:00
Evan Cheng
0ddff1b535
Compute feature bits at time of MCSubtargetInfo initialization.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 07:07:08 +00:00
Bill Wendling
b99e412650
Use ArrayRef instead of a std::vector&.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 04:42:01 +00:00
Evan Cheng
39dfb0ff84
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 03:55:05 +00:00
Bill Wendling
6a6b8c3e96
Add a target hook to encode the compact unwind information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:54:13 +00:00
Evan Cheng
94ca42ff04
Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:08:19 +00:00
Evan Cheng
78a9f138ae
Add ARM MC registry routines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:02:34 +00:00
Evan Cheng
ed5e355214
Rename files for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134546 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:01:53 +00:00
Jim Grosbach
d1689ae4b1
Mark ARM pseudo-instructions as isPseudo.
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This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134540 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 21:35:46 +00:00
Jim Grosbach
d378b32382
Remove un-used encoding info from Pseudo MLAv5.
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Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134533 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 20:57:35 +00:00
Bill Wendling
486dd90696
Constify getCompactUnwindRegNum.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 20:33:48 +00:00
Evan Cheng
b262799d49
createMCInstPrinter doesn't need TargetMachine anymore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 19:45:42 +00:00
Kevin Enderby
d521f2d2f1
Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
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push with a small constant produces a 2-byte push.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 17:23:46 +00:00
Evan Cheng
68ae5b4bea
Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 02:02:33 +00:00
Eli Friedman
af45b3d8cb
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 18:21:20 +00:00
Jim Grosbach
bc20e4f2dc
ARM estimateStackSize() needs to account for simplified call frames.
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If the function allocates reserved stack space for callee argument frames,
estimateStackSize() needs to account for that, as it doesn't show up as
ordinary frame objects. Otherwise, a callee with a large argument list will
throw off the calculations for whether to allocate an emergency spill slot
and we get assert() failures in the register scavenger.
rdar://9715469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 16:05:50 +00:00
Roman Divacky
cbb11869c4
Remove accidentaly left node from previous iteration of the patch.
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Noticed by Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-04 15:42:45 +00:00
Roman Divacky
b272332e61
Make the i64 and f64 be 64bit ABI aligned in the target description.
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This is what both the ABI and clang says.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-03 16:24:07 +00:00
Duncan Sands
d6b98e8bd8
Remove unused array.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 16:36:24 +00:00
Jakob Stoklund Olesen
0d3d95662f
Consistent diagnostic capitalization and redundant context elimination.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 07:23:40 +00:00
Jakob Stoklund Olesen
d519de0827
Include a source location when complaining about bad inline assembly.
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Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.
This enables proper clang diagnostics from the backend:
$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
__asm__ ("" : "=u" (d)); /* { dg-error "output regs" } */
^
1 error generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134307 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 03:53:34 +00:00
Eric Christopher
e3997d40de
TargetConstant immediates won't be placed into registers so tighten
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up the valid constant check earlier.
rdar://9692967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 23:04:38 +00:00
Evan Cheng
385e930d55
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 22:36:09 +00:00
Evan Cheng
ce795dc92f
Add MCSubtargetInfo target registry stuff.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134279 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 22:25:04 +00:00
Eli Friedman
adebeeaaee
Calling-convention specifications for illegal types are no-ops. Simplify based on this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 21:33:28 +00:00
Jim Grosbach
a7603982db
ARMv7M vs. ARMv7E-M support.
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The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."
Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.
rdar://9572992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 21:12:19 +00:00
Evan Cheng
5b1b4489cf
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 21:01:15 +00:00
Evan Cheng
94214703d9
- Added MCSubtargetInfo to capture subtarget features and scheduling
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itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 20:45:01 +00:00
Jim Grosbach
eb03c3b228
Fix off-by-one error.
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(low two bits always zero, so off by one bit of encoded value).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 19:07:09 +00:00
Evan Cheng
4db3cffe94
Hide the call to InitMCInstrInfo into tblgen generated ctor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 17:57:27 +00:00
Jim Grosbach
efeedceb41
Pseudo-ize t2MOVCC[ri].
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t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 17:14:11 +00:00
Akira Hatanaka
c4f24eb584
Improve Mips back-end's handling of DBG_VALUE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:04:43 +00:00
Eric Christopher
5e653c925c
Add support for the 'j' immediate constraint. This is conditionalized on
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supporting the instruction that the constraint is for 'movw'.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:00:07 +00:00
Eric Christopher
d5dc9eca2b
Add support for the ARM 't' register constraint. And another testcase
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for the 'x' register constraint.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:30:46 +00:00
Eric Christopher
1070f82569
We'll return a null RC by default if we can't match.
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Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:19:27 +00:00
Eric Christopher
89bd71fc53
Add support for the 'x' constraint.
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Part of rdar://9307836 and rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:14:47 +00:00