Andrew Trick
47c144505b
misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
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ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.
ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.
ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.
Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.
- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.
- Added ScheduleDAGInstrs::begin()/end() public API.
- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:52 +00:00
Andrew Trick
7b58ae77ac
ScheduleDAGInstrs comments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:47 +00:00
Andrew Trick
84b454d1a2
misched preparation: modularize schedule emission.
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ScheduleDAG has nothing to do with how the instructions are scheduled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:44 +00:00
Andrew Trick
73ba69b684
misched preparation: modularize schedule printing.
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ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:40 +00:00
Andrew Trick
4c72720427
misched preparation: modularize schedule verification.
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ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:36 +00:00
Andrew Trick
dbdca36af8
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:32 +00:00
Craig Topper
d3c9d9447e
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152202 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:17:23 +00:00
Eli Friedman
bb9dbb7d6b
Missing change in r152106 for TinyPtrVector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152201 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 03:37:32 +00:00
Chandler Carruth
eea81f32cd
Switch this code to use hash_combine_range rather than incremental calls
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to hash_combine. One of the interfaces could already do this, and the
other can just use a small buffer. This is a much more efficient way to
use the hash_combine interface, although I don't have any particular
benchmark where this code was hot, so I can't measure much of an impact.
It at least doesn't slow anything down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152200 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 03:22:32 +00:00
Chandler Carruth
f8cde7388e
Cache the sized-ness of struct types, once we reach the steady state of
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"is sized". This prevents every query to isSized() from recursing over
every sub-type of a struct type. This could get *very* slow for
extremely deep nesting of structs, as in 177.mesa.
This change is a 45% speedup for 'opt -O2' of 177.mesa.linked.bc, and
likely a significant speedup for other cases as well. It even impacts
-O0 cases because so many part of the code try to check whether a type
is sized.
Thanks for the review from Nick Lewycky and Benjamin Kramer on IRC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152197 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 02:33:09 +00:00
Chandler Carruth
344224b3a3
Remove an accidental cut/paste of a comment into the middle of
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a function. Dunno how I missed this when going through code...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 02:33:06 +00:00
Nick Lewycky
891495e676
No functionality change. Type::isSized() can be expensive, so avoid calling it
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until after other inexpensive tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 02:27:53 +00:00
Jim Grosbach
05d88f4fea
ARM pre-v6 assembly parsing for umull/smull.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 01:09:17 +00:00
Jim Grosbach
0104dd3ffd
ARM pre-v6 alias for 'nop' to 'mov r0, r0'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:52:41 +00:00
Jim Grosbach
ff3164a189
Tidy up. Remove dead code that slipped into previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:52:39 +00:00
Andrew Trick
255cd51fbd
Added -view-background to avoid waiting for each GraphViz invocation.
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GV and XDOT paths are untested but should work the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:27 +00:00
Andrew Trick
0df7f8821c
Added -view-misched=dags options.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:25 +00:00
Andrew Trick
56b94c52c9
Cleanup in preparation for misched: Move DAG visualization logic.
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Soon, ScheduleDAG will not refer to the BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:22 +00:00
Andrew Trick
8ceaa660bf
Added MachineBasicBlock::getFullName() to standardize/factor codegen diagnostics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:18 +00:00
Andrew Trick
acddd4963d
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:15 +00:00
Andrew Trick
084e179f09
Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:12 +00:00
Andrew Trick
e75537a243
misched comments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:08 +00:00
Andrew Trick
6cfb14f6df
misched: Use the StartBlock/FinishBlock hooks
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:05 +00:00
Eric Christopher
8938895a83
Add the DW_AT_APPLE_runtime_class attribute to forward declarations
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as well as completely defined classes.
This fixes rdar://10956070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:15:19 +00:00
Evan Cheng
03be3622aa
Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 23:33:32 +00:00
Jim Grosbach
4d0983a4d7
ARM more NEON VLD/VST composite physical register refactoring.
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Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 23:10:38 +00:00
Jakob Stoklund Olesen
c511c2827d
Hoist common code out of if statement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 22:27:13 +00:00
Jim Grosbach
c0fc450f07
ARM refactor more NEON VLD/VST instructions to use composite physregs
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Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 22:01:44 +00:00
Owen Anderson
40530ad3a8
Fix support for encodings up to 64-bits in length. TableGen was silently truncating them to 32-bits prior to this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 21:48:32 +00:00
Benjamin Kramer
2945a32ffd
SmallPtrSet: Provide a more efficient implementation of swap than the default triple-copy std::swap.
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This currently assumes that both sets have the same SmallSize to keep the implementation simple,
a limitation that can be lifted if someone cares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 20:40:02 +00:00
Eli Friedman
54427e5219
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 19:58:46 +00:00
Ted Kremenek
f0a68131de
Add new load commands for MachO.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152135 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 19:54:44 +00:00
Daniel Dunbar
956690508c
build/Darwin: Make it easy to cause all tools to get codesigned (with make CODESIGN_TOOLS=1).
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- On OS X 10.7+ this is apparently recommended practice. This maybe should
become a configurey thing one day, but I'm not sure it is right to
automatically turn it on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152133 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 19:07:38 +00:00
Jim Grosbach
bde1b2a5a8
Tidy up. Kill some dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 18:59:19 +00:00
Jakob Stoklund Olesen
14f87e01ca
Allow the same types in DPair as in QPR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 18:44:11 +00:00
Kevin Enderby
158c8a49c2
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 18:33:12 +00:00
Roman Divacky
e46137f498
Convert PowerPC to register mask operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 16:41:49 +00:00
Benjamin Kramer
e6f1355c38
Remove excess const, a const_iterator shouldn't be const itself.
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Fixes 1242 warnings from gcc during clang build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152120 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 13:32:36 +00:00
Jay Foad
4e3e5dec1a
Change ConstantAggrUniqueMap to use Chandler's new hashing
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implementation. Patch by Meador Inge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 10:43:52 +00:00
Bill Wendling
b3ef2230ff
Add column width.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152115 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 09:23:25 +00:00
Bill Wendling
cf1f6c8a37
Remove short tag marker.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 09:22:03 +00:00
Bill Wendling
63f5a1f4d6
Appease the HTML validation gods.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152113 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 09:20:59 +00:00
Bill Wendling
0eb5914411
Fix validation errors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152112 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 09:17:39 +00:00
Bill Wendling
a0edecf191
Fix validation errors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152111 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 09:17:04 +00:00
Bill Wendling
88a6808377
Add missing end tags.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 08:59:13 +00:00
Argyrios Kyrtzidis
bb07f21c76
[TinyPtrVector] Add erase method and const-goodness.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 07:14:58 +00:00
Argyrios Kyrtzidis
0db235a2b0
PointerUnion::getAddrOf() does not need to be template since we can only
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use the first pointer type for it. Rename it to getAddrOfPtr1().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 07:14:54 +00:00
Craig Topper
f0c094b115
Use uint16_t to store indices into string table since C++ only allows 64K string literals so the index into the big string can never be larger than that.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 06:04:39 +00:00
Craig Topper
904a01820c
Add asserts to ensure that values will fit into the tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 04:39:52 +00:00
Craig Topper
aff18aee56
Increase number of allowed registers in register classes to 64k instead of 256. Widen register class ID to 16-bits. Widen register size and alignment to be up to 64k bytes instead of 256 bytes. This partially reverts r152019 to be less restrictive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 03:44:22 +00:00