Commit Graph

16 Commits

Author SHA1 Message Date
Cameron Zwarich
899eaa3569 Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:52:04 +00:00
Daniel Dunbar
950d3db5f4 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
created from the", it broke some GCC test suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:30:30 +00:00
Cameron Zwarich
592ca3fda9 Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 04:54:27 +00:00
Bob Wilson
4711d5cda3 Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:02:37 +00:00
Evan Cheng
089751535d Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 18:09:28 +00:00
Evan Cheng
134982daa9 More accurate estimate / tracking of register pressure.
- Initial register pressure in the loop should be all the live defs into the
  loop. Not just those from loop preheader which is often empty.
- When an instruction is hoisted, update register pressure from loop preheader
  to the original BB.
- Treat only use of a virtual register as kill since the code is still SSA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116956 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20 22:03:58 +00:00
Rafael Espindola
1e81966626 Remove arm_apcscc from the test files. It is the default and doing this
matches what llvm-gcc and clang now produce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 15:18:27 +00:00
Evan Cheng
30fdb5c2ac - Clean up some crappy code which deals with coalescing of copies which look at
extract_subreg / insert_subreg, etc.
- Add support for more aggressive insert_subreg coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 00:44:22 +00:00
Jakob Stoklund Olesen
4a540f0593 Reapply coalescer fix for better cross-class coalescing.
This time with fixed test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-11 23:55:29 +00:00
Jim Grosbach
77b02beb1f move fconst[sd] to UAL. <rdar://7414913>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23 21:08:25 +00:00
Evan Cheng
4aedb61d03 Remat VLDRD from constpool. Clean up some instruction property specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20 19:57:15 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 00:11:35 +00:00
Evan Cheng
ba908640b3 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 05:52:54 +00:00
Anton Korobeynikov
7b360e7f29 Temporary xfail until PR5367 will be resolved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85848 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03 00:37:36 +00:00
Jim Grosbach
8cd0a8cb82 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
them for scalar floating point operations for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31 22:57:36 +00:00
Evan Cheng
21a45557c6 Add a couple of ARM cross-rc coalescing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85051 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25 08:01:41 +00:00