6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-28 22:29:56 +00:00
Code Issues Projects Releases Wiki Activity
104,605 Commits 39 Branches 0 Tags 277 MiB
4ecff11794
Commit Graph

94 Commits

Author SHA1 Message Date
Cameron McInally
998d8f50a7 Add AVX512 masked leadz instrinsic support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210652 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 12:54:45 +00:00
Adam Nemet
8dea1c4167 [X86] AVX512: Add vmovntdqa 
Along with the corresponding intrinsic and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 16:39:53 +00:00
Elena Demikhovsky
1cec507d6d AVX-512: changes in intrinsics 
1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed.
2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012).
3) I added gather/scatter prefetch intrinsics.
4) I fixed MRMm encoding for masked instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208522 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 07:18:51 +00:00
Elena Demikhovsky
8a3751f813 AVX-512: minor change in rndscale intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207937 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-04 13:35:37 +00:00
Elena Demikhovsky
e3e08acd09 AVX-512: optimized a shuffle pattern to VINSERTI64x4. 
Added intrinsics for VPERMT2PS/PD/D/Q instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207513 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-29 09:09:15 +00:00
Elena Demikhovsky
b84cc10c3c AVX-512: store and truncstore for i1 values 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206897 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-22 14:13:10 +00:00
Robert Khasanov
c13297fa76 [AVX512] Implemented integer conversions up/down with masking. 
Added encoding tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206884 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-22 11:36:19 +00:00
Filipe Cabecinhas
c5b286bc41 Rename X86insrtps to the proper instruction name. 
Summary:
The INSERTPS pattern fragment was called insrtps (mising 'e'), which
would make it harder to grep for the patterns related to this instruction.
Renaming it to use the proper instruction name.

Reviewers: nadav

CC: llvm-commits

Differential Revision: http://reviews.llvm.org/D3443

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206779 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-21 20:07:29 +00:00
Elena Demikhovsky
0d5d656524 AVX-512: insert element to mask vector; store i1 data 
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205850 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 12:37:50 +00:00
Elena Demikhovsky
dbcb670605 AVX-512: Added fp_to_uint and uint_to_fp patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205754 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-08 07:24:02 +00:00
Robert Khasanov
fe6e1e9b3c Test commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205214 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 16:01:38 +00:00
Elena Demikhovsky
61785a0c3d AVX-512: Implemented masking for integer arithmetic & logic instructions. 
By Robert Khasanov rob.khasanov@gmail.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204906 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-27 09:45:08 +00:00
Cameron McInally
4de1039403 Fix AVX512 Gather and Scatter execution domains. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204804 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-26 13:50:50 +00:00
Elena Demikhovsky
3d1ae71813 AVX-512: masked load/store + intrinsics for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203790 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-13 12:05:52 +00:00
Elena Demikhovsky
b0a3627443 AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP packed instructions, added encoding tests for them. 
By Robert Khazanov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203098 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-06 08:45:30 +00:00
Elena Demikhovsky
a9fe27ffb3 AVX-512: Fixed extract_vector_elt for v8i1 vector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202624 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-02 09:19:44 +00:00
Elena Demikhovsky
58423c8f1a AVX-512: Fixed encoding of VPCMPEQ and VPCMPGT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202015 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-24 10:08:30 +00:00
Elena Demikhovsky
73f1a5fe45 AVX-512: Fixed encoding of VPTESTMQ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201980 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-23 14:28:35 +00:00
Elena Demikhovsky
08316a11e4 AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com) 
Fixed truncate i32 to i1; a test will be provided in the next commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201757 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-20 06:34:39 +00:00
Cameron McInally
35f15e54a9 Fix AVX512 vector sqrt assembly strings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201681 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-19 15:16:09 +00:00
Craig Topper
7d2bb38164 Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201538 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-18 00:21:49 +00:00
Elena Demikhovsky
e139a1e0e4 AVX-512: implemented zext fron i1 to i16 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201502 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-17 07:29:33 +00:00
Elena Demikhovsky
f280c65b32 AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequence 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201487 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-16 11:34:23 +00:00
Elena Demikhovsky
e4092e9895 AVX-512: Optimized BUILD_VECTOR pattern; 
fixed encoding of VEXTRACTPS instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201134 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-11 07:25:59 +00:00
Elena Demikhovsky
27ef6eec41 AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201066 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 07:02:39 +00:00
Elena Demikhovsky
002683abc7 AVX-512: Added intrinsic for cvtph2ps. 
Added VPTESTNM instruction.
Added a pattern to vselect (lit tests will follow).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200823 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-05 07:05:03 +00:00
Craig Topper
312eec7ecb Simplify some x86 format classes and remove some ambiguities in their application. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200608 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-01 08:17:56 +00:00
Craig Topper
db752405cb Remove duplicate pattern and add predicate checks on other patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200455 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-30 06:03:19 +00:00
Elena Demikhovsky
e1a621d84f AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions, 
they give better sequences than VPERMI


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199893 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-23 14:27:26 +00:00
Elena Demikhovsky
d05a6582da AVX-512: optimized scalar compare patterns 
removed AVX512SI format, since it is similar to AVX512BI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199217 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 15:10:08 +00:00
Craig Topper
525ae45240 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 07:41:20 +00:00
Elena Demikhovsky
1f044d443d AVX-512: Embedded Rounding Control - encoding and printing 
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-13 12:55:03 +00:00
Elena Demikhovsky
958cc01fff AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198745 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 10:54:22 +00:00
Elena Demikhovsky
a56ae89d22 AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198593 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-06 08:45:54 +00:00
Elena Demikhovsky
497417520c AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD; 
Optimized a truncate pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198562 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 14:21:07 +00:00
Elena Demikhovsky
3a880de6e6 AVX-512: Added more intrinsics for convert and min/max. 
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198557 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 10:46:09 +00:00
Craig Topper
01cb7fa977 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:55:55 +00:00
Craig Topper
527f132627 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:17:28 +00:00
Craig Topper
e625100c6a Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198323 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 17:28:14 +00:00
Elena Demikhovsky
3062a311ac AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-01 15:12:34 +00:00
Elena Demikhovsky
fab5704cef AVX-512: Result type of scalar SETCC is MVT::i1 for AVX-512. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198008 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-25 10:06:40 +00:00
Elena Demikhovsky
097935cc40 AVX-512: fixed some patterns for MVT::i1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197981 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-24 14:24:07 +00:00
Elena Demikhovsky
cd70023007 AVX512: SETCC returns i1 for AVX-512 and i8 for all others 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197876 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-22 10:13:18 +00:00
Elena Demikhovsky
1f0a0e314d AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey Bader). 
Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197482 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-17 08:33:15 +00:00
Elena Demikhovsky
376a81d8ce AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky
3bf51cf302 AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC. 
I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197041 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 14:31:04 +00:00
Elena Demikhovsky
8a8581ca4b AVX-512: changed intrinsics for mask operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196918 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 13:53:10 +00:00
Elena Demikhovsky
89458ced87 AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin form 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196914 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 11:58:35 +00:00
Cameron McInally
febc28b529 Update AVX512 vector blend intrinsic names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196581 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-06 13:35:35 +00:00
Cameron McInally
6c8faddaf5 Add AVX512 patterns for v16i32 broadcast and v2i64 zero extend load. 
Patch by Aleksey Bader.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196435 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-05 00:11:25 +00:00