Commit Graph

92185 Commits

Author SHA1 Message Date
Reed Kotler
eafa96485a This is the first of three patches which creates stubs used for
Mips16/32 floating point interoperability.

When Mips16 code calls external functions that would normally have some
of its parameters or return values passed in floating point registers,
it needs (Mips32) helper functions to do this because while in Mips16 mode
there is no ability to access the floating point registers.

In Pic mode, this is done with a set of predefined functions in libc.
This case is already handled in llvm for Mips16.

In static relocation mode, for efficiency reasons, the compiler generates
stubs that the linker will use if it turns out that the external function
is a Mips32 function. (If it's Mips16, then it does not need the helper
stubs).

These stubs are identically named and the linker knows about these tricks
and will not create multiple copies and will delete them if they are not
needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 02:00:24 +00:00
Akira Hatanaka
dd29df06fa StackColoring: don't clear an instruction's mem operand if the underlying
object is a PseudoSourceValue and PseudoSourceValue::isConstant returns true (i.e.,
points to memory that has a constant value).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 01:42:44 +00:00
David Blaikie
17a692e7f1 Assert that DIEEntries are constructed with non-null DIEs
This just brings a crash a little further forward from DWARF emission to
DIE construction to make errors easier to diagnose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181748 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 00:35:19 +00:00
Arnold Schwaighofer
123f18bcb9 LoopVectorize: Handle loops with multiple forward inductions
We used to give up if we saw two integer inductions. After this patch, we base
further induction variables on the chosen one like we do in the reverse
induction and pointer induction case.

Fixes PR15720.

radar://13851975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 00:21:18 +00:00
Michael Gottesman
dba53a8c9d [objc-arc-opts] Added debug statements when we set and unset whether a pointer is known positive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 00:08:09 +00:00
Michael Gottesman
acfb3584c5 [objc-arc-opts] In the presense of an alloca unconditionally remove RR pairs if and only if we are both KnownSafeBU/KnownSafeTD rather than just either or.
In the presense of a block being initialized, the frontend will emit the
objc_retain on the original pointer and the release on the pointer loaded from
the alloca. The optimizer will through the provenance analysis realize that the
two are related (albiet different), but since we only require KnownSafe in one
direction, will match the inner retain on the original pointer with the guard
release on the original pointer. This is fixed by ensuring that in the presense
of allocas we only unconditionally remove pointers if both our retain and our
release are KnownSafe (i.e. we are KnownSafe in both directions) since we must
deal with the possibility that the frontend will emit what (to the optimizer)
appears to be unbalanced retain/releases.

An example of the miscompile is:

  %A = alloca
  retain(%x)
  retain(%x) <--- Inner Retain
  store %x, %A
  %y = load %A
  ... DO STUFF ...
  release(%y)
  call void @use(%x)
  release(%x) <--- Guarding Release

getting optimized to:

  %A = alloca
  retain(%x)
  store %x, %A
  %y = load %A
  ... DO STUFF ...
  release(%y)
  call void @use(%x)

rdar://13750319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 23:49:42 +00:00
Matt Beaumont-Gay
9b5e6c0943 Move a couple more statistics inside '#ifndef NDEBUG'.
Suppresses an unused-variable warning in -Asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 21:10:49 +00:00
Jack Carter
f4a1377322 Mips assembler: Assembler macro ADDIU $rs,imm
This patch adds alias for addiu instruction which enables following syntax:

    addiu $rs,imm

The macro is translated as:

    addiu $rs,$rs,imm


Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 20:26:46 +00:00
Michael Gottesman
774a8cf2f5 [objc-arc-opts] Add comment to BBState making it clear that get{TopDown,BottomUp}PtrState will create a new PtrState object if it does not find a PtrState for Arg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181726 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 19:40:39 +00:00
Bill Schmidt
59b078fc56 Fix goofy commentary in PPCTargetObjectFile.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 19:40:36 +00:00
Bill Schmidt
240b9b6078 PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.
This fixes warning messages observed in the oggenc application test in
projects/test-suite.  Special handling is needed for the 64-bit
PowerPC SVR4 ABI when a constant is initialized with a pointer to a
function in a shared library.  Because a function address is
implemented as the address of a function descriptor, the use of copy
relocations can lead to problems with initialization.  GNU ld
therefore replaces copy relocations with dynamic relocations to be
resolved by the dynamic linker.  This means the constant cannot reside
in the read-only data section, but instead belongs in .data.rel.ro,
which is designed for constants containing dynamic relocations.

The implementation creates a class PPC64LinuxTargetObjectFile
inheriting from TargetLoweringObjectFileELF, which behaves like its
parent except to place constants of this sort into .data.rel.ro.

The test case is reduced from the oggenc application.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 19:34:37 +00:00
Bob Wilson
a753ff72b2 Remove redundant variable introduced by r181682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 19:02:31 +00:00
Michael Gottesman
fa709768b9 [objc-arc] Move the before optimization statistics gathering phase out of OptimizeIndividualCalls.
This makes the statistics gathering completely independent of the actual
optimization occuring, preventing any sort of bleeding over from occuring.

Additionally, it simplifies a switch statement in the non-statistic gathering case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181719 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 18:29:07 +00:00
Akira Hatanaka
42f562a169 [mips] Add option -mno-ldc1-sdc1.
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 18:23:35 +00:00
Shuxin Yang
4b6b53b0ce Fix a bug that APFloat::fusedMultiplyAdd() mistakenly evaluate "14.5f * -14.5f + 225.0f" to 225.0f.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 18:03:12 +00:00
Akira Hatanaka
151687cb8c [mips] Define a helper function which creates an instruction with the same
operands as the prototype instruction but with a different opcode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181714 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 17:57:42 +00:00
Akira Hatanaka
6daba28683 [mips] Rename functions. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 17:43:19 +00:00
Rafael Espindola
6eb70ac034 Remove unused fields and arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 14:34:48 +00:00
Mihai Popa
f86e436fb9 The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 14:10:04 +00:00
Lang Hames
d26c93d3a8 Correctly preserve the input chain for potential tailcall nodes whose
return values are bitcasts.

The chain had previously been being clobbered with the entry node to
the dag, which sometimes caused other code in the function to be
erroneously deleted when tailcall optimization kicked in.

<rdar://problem/13827621>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181696 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 10:21:19 +00:00
Duncan Sands
b99052ce4a Suppress GCC compiler warnings in release builds about variables that are only
read in asserts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 07:50:47 +00:00
Nadav Rotem
985eb9004c SLPVectorizer: Swap LHS and RHS. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181684 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 05:13:13 +00:00
Hao Liu
3778c04b2e Fix PR15950 A bug in DAG Combiner about undef mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 02:07:05 +00:00
Rafael Espindola
4a971705bc Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 01:16:13 +00:00
Rafael Espindola
aa4f36407f XFAIL this test for mingw too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181678 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 00:18:24 +00:00
Nadav Rotem
507b9242ed SLPVectorizer: Fix a bug in the code that generates extracts for values with multiple users.
The external user does not have to be in lane #0. We have to save the lane for each scalar so that we know which vector lane to extract.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-12 22:58:45 +00:00
Nadav Rotem
57e02b3358 SLPVectorizer: Clear the map that maps between scalars to vectors after each round of vectorization.
Testcase in the next commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181673 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-12 22:55:57 +00:00
David Majnemer
fa49d7d6e4 InstCombine: Flip the order of two urem transforms
There are two transforms in visitUrem that conflict with each other.

*) One, if a divisor is a power of two, subtracts one from the divisor
   and turns it into a bitwise-and.
*) The other unwraps both operands if they are surrounded by zext
   instructions.

Flipping the order allows the subtraction to go beneath the sign
extension.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181668 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-12 00:07:05 +00:00
Arnold Schwaighofer
9b5d70f076 LoopVectorize: Use the widest induction variable type
Use the widest induction type encountered for the cannonical induction variable.

We used to turn the following loop into an empty loop because we used i8 as
induction variable type and truncated 1024 to 0 as trip count.

int a[1024];
void fail() {
  int reverse_induction = 1023;
  unsigned char forward_induction = 0;
  while ((reverse_induction) >= 0) {
    forward_induction++;
    a[reverse_induction] = forward_induction;
    --reverse_induction;
  }
}

radar://13862901

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 23:04:28 +00:00
Arnold Schwaighofer
6bb539a643 LoopVectorize: Use variable instead of repeated function call
No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181666 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 23:04:26 +00:00
Arnold Schwaighofer
8112d22701 LoopVectorize: Use IRBuilder interface in more places
No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181665 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 23:04:24 +00:00
David Blaikie
13b11cd810 Correct parameter name in doc comment to match declaration.
(review feedback on r181632 from Dmitri)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 19:14:10 +00:00
Benjamin Kramer
03406c4f15 StringRefize some debug accel table bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181663 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 18:24:28 +00:00
David Majnemer
a8ccefc0a3 InstCombine: Turn urem to bitwise-and more often
Use isKnownToBeAPowerOfTwo in visitUrem so that we may more aggressively
fold away urem instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181661 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 09:01:28 +00:00
Rafael Espindola
d84ccfaf50 Change getFrameMoves to return a const reference.
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 02:38:11 +00:00
Rafael Espindola
baf81af759 Remove more dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 02:24:41 +00:00
Reed Kotler
a6e31cf69e Add -mtriple=mipsel-linux-gnu to the test so that the compiler does
not think it can support small data sections.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181654 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11 01:02:20 +00:00
Rafael Espindola
01a21b3379 Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181649 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 23:34:51 +00:00
Nadav Rotem
9bba9f6300 SLPVectorizer: Add support for trees with external users.
For example:
bar() {
  int a = A[i];
  int b = A[i+1];
  B[i] = a;
  B[i+1] = b;
  foo(a);  <--- a is used outside the vectorized expression.
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181648 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:59:33 +00:00
Nadav Rotem
09ec4b2164 Add a debug print
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181647 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:56:18 +00:00
Nadav Rotem
ef3e423e23 Add an additional testcase for PR15882.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181646 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:55:44 +00:00
Reed Kotler
46090914b7 Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability. 

This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.

Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.

This is needed when returning float, double, single complex, double complex
in the Mips ABI.

Helper functions in libc for mips16 are available to do this.

For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.

Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.

This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.

The only register that is modified is ra in this call.

The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
Jordan Rose
1197e38f33 Micro-optimization: don't shift an entire bitcode record over to get the code.
Previously, BitstreamCursor read an abbreviated record by splatting the
whole thing into a data vector, then extracting and removing the /first/
element. Now, it reads the first element--the record code--separately from
the actual field values.

No (intended) functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181639 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:17:10 +00:00
David Blaikie
acd1d031b8 Give the test from r181632 a target triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:14:39 +00:00
David Blaikie
4de9d72883 PR14492: Debug Info: Support for values of non-integer non-type template parameters.
This is only tested for global variables at the moment (& includes tests
for the unnamed parameter case, since apparently this entire function
was completely untested previously)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 21:52:07 +00:00
Jyotsna Verma
fd4ccda4a5 Fix unused variable error.
Earlier, this variable was used in an assert and was causing failure on
darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181630 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 21:44:02 +00:00
Jyotsna Verma
cdfb55d15b Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181628 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 20:58:11 +00:00
Jyotsna Verma
1a35b8e2eb Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 20:27:34 +00:00
Rafael Espindola
ed9fc9b8ee Fix the R600 build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181621 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 18:31:42 +00:00
Chad Rosier
ffc49cbea4 [ms-inline asm] Fix a crasher when we fail on a direct match.
The issue was that the MatchingInlineAsm and VariantID args to the
MatchInstructionImpl function weren't being set properly.  Specifically, when
parsing intel syntax, the parser thought it was parsing inline assembly in the
at&t dialect; that will never be the case.  

The crash was caused when the emitter tried to emit the instruction, but the
operands weren't set.  When parsing inline assembly we only set the opcode, not
the operands, which is used to lookup the instruction descriptor.
rdar://13854391 and PR15945

Also, this commit reverts r176036.  Now that we're correctly parsing the intel
syntax the pushad/popad don't match properly.  I've reimplemented that fix using
a MnemonicAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 18:24:17 +00:00