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Author SHA1 Message Date
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:48:45 +00:00
Bruno Cardoso Lopes
18deb04e9c Add v16i16 and v32i8 store patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137166 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:39:53 +00:00
Chad Rosier
6ff9aa2aa7 Fix 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:23:40 +00:00
Rafael Espindola
dd3d68f7a9 Add missing file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137162 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:19:52 +00:00
Bruno Cardoso Lopes
cde4a1abd5 Use fp unpack instructions to unpack int types. Until we have AVX2, this 
is the best we can do for these patterns. This fix PR10554.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:18:37 +00:00
Eli Friedman
fc430a662f Fix a couple ridiculous copy-paste errors. rdar://9914773 . 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:17:39 +00:00
Rafael Espindola
69cb216009 Add a C interface to PassManagerBuilder. It is missing the addExtension 
functionality since in the C api a pass is created and added to a pass
manager in a single call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137159 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:17:34 +00:00
Jim Grosbach
739b5576ad Don't truncate MachO addresses. 
Assigned symbol addresses get truncated to 32-bits, even on 64-bit platforms.
That's obviously bogus.
For example,

 .globl _foo
 .equ _foo, 0x987654321ULL


rdar://9922863



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:12:37 +00:00
Benjamin Kramer
793b811c50 ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:02:50 +00:00
Owen Anderson
51157d2234 Silence an false-positive warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:38:14 +00:00
Owen Anderson
65e95d950d Don't generate the old-style disassembler in CMake builds either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:36:11 +00:00
Benjamin Kramer
9bd7c2836e The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:34:19 +00:00
Owen Anderson
ad0d36b79f Don't continue generating the old-style decoder file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137150 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:30:29 +00:00
Jim Grosbach
6cd5716f61 ARM fix typo in pre-indexed store lowering. 
rdar://9915869


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:22:41 +00:00
Owen Anderson
e6afbabb63 Attempt to fix CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:09:59 +00:00
Owen Anderson
bd9091c18d Tighten Thumb1 branch predicate decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:07:45 +00:00
Eli Friedman
138515df66 First draft of the practical guide to atomics. 
This is mostly descriptive of the intended state once atomic load and store have landed.  



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137145 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:07:10 +00:00
Owen Anderson
8d7d2e1238 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 20:55:18 +00:00
Bob Wilson
0dc8b42987 Put Darwin-specific code inside an __APPLE__ ifdef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 19:54:32 +00:00
Bill Wendling
c6fbe5636d Revert r137134. It breaks some code as Eli pointed out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 18:56:35 +00:00
Bill Wendling
a0f596c1fc Print out the variable declaration only if it is a declaration. Otherwise, a 
'static' variable will be emitted twice.
PR10081


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 18:31:50 +00:00
Jakob Stoklund Olesen
4a74b3b933 Inflate register classes after coalescing. 
Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class.  Examples are:

  x86: GR32_ABCD:sub_8bit_hi -> GR32
  arm: DPR_VFP2:ssub0 -> DPR

Recompute the register class of any virtual registers that are used by
less instructions after coalescing.

This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:

  vadd.f32  d16, d1, d0
  vcvt.s32.f32  d0, d16

The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 18:19:41 +00:00
Bruno Cardoso Lopes
e2406dfd89 Reapply a more appropriate solution than in r137114. AVX supports 
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137128 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes
a511b8e519 Revert r137114 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:39:01 +00:00
Justin Holewinski
4bdd4ed564 PTX: Add initial support for device function calls 
- Calls are supported on SM 2.0+ for function with no return values

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:36:31 +00:00
Jakob Stoklund Olesen
6d1fd0b979 Move CalculateRegClass to MRI::recomputeRegClass. 
This function doesn't have anything to do with spill weights, and MRI
already has functions for manipulating the register class of a virtual
register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 16:46:27 +00:00
Renato Golin
719927a68f Emitting ARM build attributes and values as ULEB, rather than char. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 09:50:10 +00:00
Bruno Cardoso Lopes
e321d7ffc5 Handle sitofp between v4f64 <- v4i32. Fix PR10559 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 05:48:01 +00:00
Bob Wilson
f5b757642d Recognize the UNAME_RELEASE environment variable to match Darwin's uname. 
When this variable is set, "uname -r" will return its value instead of the
real OS version.  Make this affect LLVM's triple for consistency.
<rdar://problem/9919167>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137111 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 05:13:36 +00:00
Andrew Trick
70d0ca999c LoopUnroll looks like it has some stale code. Remove it to prove my sanity and avoid further confusion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:11:29 +00:00
Bruno Cardoso Lopes
2f613c5fff Add support for avx vector fextend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes
a1dfb63b78 Add AVX versions of 128-bit sitofp and fptosi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:25 +00:00
Bruno Cardoso Lopes
b33ea56448 Rename and tidy up tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:23 +00:00
Bruno Cardoso Lopes
e5118ab7bb Add two patterns to match special vmovss and vmovsd cases. Also fix 
the patterns already there to be more strict regarding the predicate.
This fixes PR10558

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:43:09 +00:00
Bill Wendling
8d676c2199 There is only one instance of this placeholder being created. Just use that 
instead of a vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:17:10 +00:00
Bill Wendling
4fa93b7ce1 Remove an instance where the 'unwind' instruction was created. 
The 'unwind' instruction was acting essentially as a placeholder, because it
would be replaced at the end of this function by a branch to the "unwind
handler". The 'unwind' instruction is going away, so use 'unreachable' instead,
which serves the same purpose as a placeholder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:09:21 +00:00
Devang Patel
a2b552d0ae Print variable's inline location in debug output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:03:35 +00:00
Devang Patel
48d726fbce Provide method to print variable's extended name which includes inline location. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:03:14 +00:00
Jakob Stoklund Olesen
c19e6dd64f Rename member variables to follow coding standards. 
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:01:27 +00:00
Bill Wendling
54f1536927 Add missing attributes to the C++ backend's output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:47:30 +00:00
Bruno Cardoso Lopes
0f0e0a0e58 Make LowerVSETCC aware of AVX types and add patterns to match them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:46:57 +00:00
Jakob Stoklund Olesen
8e0cca6945 Move the RegisterCoalescer private to its implementation file. 
RegisterCoalescer.h still has the CoalescerPair class interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:43:37 +00:00
Dan Gohman
8db7353246 Tidy up these testcases to look more like real code does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:33:11 +00:00
Jakob Stoklund Olesen
27215676c7 Refer to the RegisterCoalescer pass by ID. 
A public interface is no longer needed since RegisterCoalescer is not an
analysis any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:29:53 +00:00
Jim Grosbach
3148a65490 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 23:28:47 +00:00
Owen Anderson
648f9a75fd Thumb1 BL instructions encoding 22 bits of displacement, not 21. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 23:25:22 +00:00
Bill Wendling
7df4f963ea Indicate that there are changes if runOfFunction returns saying that there are. 
Patch by Jingyue!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137072 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 23:01:10 +00:00
Jim Grosbach
bc6fc20fcc ARM parsing and encoding for LDRB instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 22:37:06 +00:00
Jim Grosbach
8668a5b0c8 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 22:11:33 +00:00
Jakob Stoklund Olesen
36ee0e6405 Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM. 
They improve the verbose assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 21:45:32 +00:00