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51c9805c4b
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13737 Commits

Author SHA1 Message Date
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:48:45 +00:00
Bruno Cardoso Lopes
18deb04e9c Add v16i16 and v32i8 store patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137166 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:39:53 +00:00
Bruno Cardoso Lopes
cde4a1abd5 Use fp unpack instructions to unpack int types. Until we have AVX2, this 
is the best we can do for these patterns. This fix PR10554.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:18:37 +00:00
Eli Friedman
fc430a662f Fix a couple ridiculous copy-paste errors. rdar://9914773 . 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:17:39 +00:00
Benjamin Kramer
793b811c50 ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:02:50 +00:00
Owen Anderson
bd9091c18d Tighten Thumb1 branch predicate decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:07:45 +00:00
Owen Anderson
8d7d2e1238 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 20:55:18 +00:00
Bill Wendling
c6fbe5636d Revert r137134. It breaks some code as Eli pointed out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 18:56:35 +00:00
Bill Wendling
a0f596c1fc Print out the variable declaration only if it is a declaration. Otherwise, a 
'static' variable will be emitted twice.
PR10081


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 18:31:50 +00:00
Jakob Stoklund Olesen
4a74b3b933 Inflate register classes after coalescing. 
Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class.  Examples are:

  x86: GR32_ABCD:sub_8bit_hi -> GR32
  arm: DPR_VFP2:ssub0 -> DPR

Recompute the register class of any virtual registers that are used by
less instructions after coalescing.

This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:

  vadd.f32  d16, d1, d0
  vcvt.s32.f32  d0, d16

The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 18:19:41 +00:00
Bruno Cardoso Lopes
e2406dfd89 Reapply a more appropriate solution than in r137114. AVX supports 
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137128 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes
a511b8e519 Revert r137114 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:39:01 +00:00
Justin Holewinski
4bdd4ed564 PTX: Add initial support for device function calls 
- Calls are supported on SM 2.0+ for function with no return values

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 17:36:31 +00:00
Bruno Cardoso Lopes
e321d7ffc5 Handle sitofp between v4f64 <- v4i32. Fix PR10559 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 05:48:01 +00:00
Bruno Cardoso Lopes
2f613c5fff Add support for avx vector fextend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes
b33ea56448 Rename and tidy up tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 03:04:23 +00:00
Bruno Cardoso Lopes
e5118ab7bb Add two patterns to match special vmovss and vmovsd cases. Also fix 
the patterns already there to be more strict regarding the predicate.
This fixes PR10558

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 01:43:09 +00:00
Bruno Cardoso Lopes
0f0e0a0e58 Make LowerVSETCC aware of AVX types and add patterns to match them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:46:57 +00:00
Dan Gohman
8db7353246 Tidy up these testcases to look more like real code does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 00:33:11 +00:00
Jim Grosbach
3148a65490 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 23:28:47 +00:00
Jim Grosbach
bc6fc20fcc ARM parsing and encoding for LDRB instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 22:37:06 +00:00
Jim Grosbach
8668a5b0c8 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 22:11:33 +00:00
Bruno Cardoso Lopes
328a9d4a0f Add support for several vector shifts operations while in AVX mode. Fix PR10581 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137067 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 21:31:08 +00:00
Eli Friedman
2cb1dfa446 Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 19:49:37 +00:00
Jakob Stoklund Olesen
66b0f515d5 Don't clobber pending ST regs when FP regs are killed. 
X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints.  It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.

When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.

This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.

This fixes PR10602.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 17:15:43 +00:00
Andrew Trick
06988bcf6a Made SCEV's UDiv expressions more canonical. When dividing a 
recurrence, the initial values low bits can sometimes be ignored.

To take advantage of this, added FoldIVUser to IndVarSimplify to fold
an IV operand into a udiv/lshr if the operator doesn't affect the
result.

-indvars -disable-iv-rewrite now transforms

i = phi i4
i1 = i0 + 1
idx = i1 >> (2 or more)
i4 = i + 4

into

i = phi i4
idx = i0 >> ...
i4 = i + 4


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-06 07:00:37 +00:00
Jim Grosbach
0d6fac36ed ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 22:03:36 +00:00
Jim Grosbach
f4fa3d6e46 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 21:28:30 +00:00
Jim Grosbach
6fc1c08635 Add ARM LDR parsing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 20:33:39 +00:00
Devang Patel
1f35b17885 We need to map DebugLoc. It leads to Fuction * (through subprogram entry node) which should be appropriately mapped. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136910 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 20:02:18 +00:00
Devang Patel
211da8f7a9 Linke NamedMDNodes after linking global values as comment suggests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136909 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 19:44:28 +00:00
Rafael Espindola
5c4e52e496 Fix the bitwidth of the remaining fields. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 17:00:11 +00:00
Rafael Espindola
251a2bbfb0 print st_shndx with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136880 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:50:13 +00:00
Rafael Espindola
67ac0c0d63 print st_other with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136877 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:38:19 +00:00
Rafael Espindola
71a8f5ca12 print st_type with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:24:00 +00:00
Rafael Espindola
d7c278326f Print st_bind with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136874 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:10:35 +00:00
Rafael Espindola
a83f8ef9b4 Print r_sym with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:48:27 +00:00
Rafael Espindola
f81f6758f3 Print r_type with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136872 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:39:30 +00:00
Rafael Espindola
65ad8dc807 Another counter goes decimal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:27:46 +00:00
Rafael Espindola
f7179de2a5 Change anther counter to decimal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136870 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:01:03 +00:00
Rafael Espindola
014180d387 Don't print a counter in hex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 13:39:15 +00:00
Rafael Espindola
d7c9b63b58 Print all the bits in the addend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136867 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 13:00:24 +00:00
Jason W Kim
e651983e71 Fix http://llvm.org/bugs/show_bug.cgi?id=10568 
Move the reloc size assert into AsmBackend - where it is more apropos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136855 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 00:38:45 +00:00
Bill Wendling
456a925c61 Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR. 
Fixes PR10527.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 00:32:58 +00:00
Jim Grosbach
7ce057983e ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 23:50:40 +00:00
Benjamin Kramer
9dbd0a866e Remove underscore that's breaking linux buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 23:13:01 +00:00
Jakub Staszak
990f78d53b Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 22:34:43 +00:00
Bill Wendling
2626dba9c5 Remove the LowerSetJmp pass. It wasn't used effectively by any of the targets. 
This is some of my original LLVM code. *wipes tear*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136821 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 22:18:20 +00:00
Andrew Trick
1009c3299b SCEV: Use AssertingVH to catch dangling BasicBlock* when passes forget 
to notify SCEV of a change. Add forgetLoop in a couple of those places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136797 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 18:32:11 +00:00
Jakob Stoklund Olesen
56e3232d5a Handle IMPLICIT_DEF instructions in X86FloatingPoint. 
This fixes PR10575.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136787 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-03 16:33:19 +00:00