so additional dep. edges have to be added.
This was needed to correctly handle conditional move instructions!
MachineCodeForBasicBlock is now an annotation on BasicBlock.
Renamed "earliestForNode" to "earliestReadyTimeForNode".
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- Rename runOnMethod to runOnFunction
* Transform getAnalysisUsageInfo into getAnalysisUsage
- Method is now const
- It now takes one AnalysisUsage object to fill in instead of 3 vectors
to fill in
- Pass's now specify which other passes they _preserve_ not which ones
they modify (be conservative!)
- A pass can specify that it preserves all analyses (because it never
modifies the underlying program)
* s/Method/Function/g in other random places as well
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* Delete the DelaySlotInfo objects created by the SchedulingManager class.
These leaked objects were accounting for 3/4 of the memory leaked by the
backend, so this is a relatively major win.
* Reorganize SchedulingManager::getDelaySlotInfoForInstr so that it has
better code locality (making it easier to read).
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class. The Method class is obsolete (renamed) and all references to it
are being converted over to Function.
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Destroy live-variable information after scheduling so it is
recomputed before later phases (e.g., reg. allocation).
Use deterministic iterator to enumerate sched graphs.
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llvm/Support/CFG.h
* Make pred & succ iterators for intervals global functions
* Add #includes that are now neccesary because BasicBlock.h doesn't include
InstrTypes.h anymore
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Method::inst_* is now in llvm/Support/InstIterator.h
GraphTraits specializations for BasicBlock and Methods are now in llvm/Support/CFG.h
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function in the one .cpp file that uses it. Use ValueSet's instead.
* Prepare to delete LiveVarSet.h & LiveVarSet.cpp
* Eliminate the ValueSet class, making all old member functions into global
templates that will eventually be moved to Support.
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* InstructionScheduling is now a real pass
* InstrSched _uses_ LiveVar analysis, instead of creating it's own copy many times
through a loop. In this was LiveVarAnalysis is actually even SHARED by Register
allocation.
* SchedPriorities is now passed the live var information in
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since some m. instr. may be generated by LLVM instrs. in other blocks.
Handle non-SSA (anti and output) edges and true edges uniformly by
working with machine instructions alone.
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This wasn't a problem until we started putting copies for Phi values
that produced cycles in the SchedGraph!
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are now found as part of the initial walk of the machine code).
Also memory load/store instructions can be generated for non-memory
LLVM instructions, which wasn't handled before. It is now.
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Avoids having to handle some special cases that cause complex interactions
with instr. selection.
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(b) any instructions that use or set CC registers. Whether or not the
latter are needed really should be machine-dependent.
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from the value itself (the one causing an edge) because the latter may be
a temporary used within the instruction sequence for the VM instruction.
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