Richard Osborne
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54d6266e9b
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Add instruction encodings and disassembly for 1r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-12-16 17:37:34 +00:00 |
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Richard Osborne
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054169be24
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Remove invalid instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170291 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-12-16 16:46:31 +00:00 |
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Richard Osborne
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1fb0aaa58f
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Mark anything deriving from PseudoInstXCore as a pseudo instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170290 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-12-16 16:46:28 +00:00 |
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Richard Osborne
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a44a751bc9
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Set instruction size correctly in XCoreInstrFormats.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170289 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-12-16 16:46:24 +00:00 |
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Jia Liu
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31d157ae1a
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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-02-18 12:03:15 +00:00 |
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Richard Osborne
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b25baef26f
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Add XCore backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58838 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-07 10:59:00 +00:00 |
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