* fold left shifts of 1, 2, 3 or 4 bits into adds
This doesn't save much now, but should get a serious workout once
multiplies by constants get converted to shift/add/sub sequences.
Hold on! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21282 91177308-0d34-0410-b5e6-96231b3b80d8
0x00000..00FFF..FF
^ ^
^ ^
any number of
0's followed by
some number of
1's
then we use dep.z to just paste zeros over the input. For the special
cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
because we're all about readability!!!
that's what it's about!! readability!
*twitch* ;D
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21279 91177308-0d34-0410-b5e6-96231b3b80d8
like this:
ldah $1,1($31)
lda $1,-1($1)
and $0,$1,$24
instead of this:
zap $0,252,$24
To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21270 91177308-0d34-0410-b5e6-96231b3b80d8
things like this:
mov r9 = 65535;;
and r8 = r8, r9;;
To be emitted instead of:
zxt2 r8 = r8;;
To get this back, the selector for ISD::AND should recognize this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21269 91177308-0d34-0410-b5e6-96231b3b80d8
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21268 91177308-0d34-0410-b5e6-96231b3b80d8
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.
FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:
out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127
and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21252 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor how . instructions are handled. In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.
For example, instead of this:
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB">;
We now have this:
+def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
* fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
* fix nasty thinko - didn't use two-address form of conditional add
for extending bools to integers, so occasionally there would be
garbage in the result. it's amazing how often zeros are just
sitting around in registers ;) - this should fix a bunch of tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21221 91177308-0d34-0410-b5e6-96231b3b80d8
correct. Remove the EmitComparison retvalue, as it is always the first arg.
Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty. Crafty now works!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21195 91177308-0d34-0410-b5e6-96231b3b80d8
This caused the "use before a def" assertion on some programs.
With this patch, 254.gap now passes with the PPC backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21191 91177308-0d34-0410-b5e6-96231b3b80d8
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21187 91177308-0d34-0410-b5e6-96231b3b80d8
* fix overallocation of integer (stacked) registers: we can't allocate
registers for local use if they are required as output registers
this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21178 91177308-0d34-0410-b5e6-96231b3b80d8
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
Pattern match fsub a, mul(b, c) as fnmsub
Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21161 91177308-0d34-0410-b5e6-96231b3b80d8
