Commit Graph

94586 Commits

Author SHA1 Message Date
Vladimir Medic
588f408b95 Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:25:27 +00:00
Tim Northover
87773c318f AArch64: add initial NEON support
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:20:35 +00:00
Robert Lytton
691aa094da XCore target: add GCCBuiltin to four intrinsics
The following are made available by clang in the XCore ABI
	__builtin_bitrev
	__builtin_getid
	__builtin_getps
	__builtin_setps

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 08:41:32 +00:00
Robert Lytton
dd1cfe2129 XCore target: Fix Vararg handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187565 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 08:29:44 +00:00
Robert Lytton
f2617291e3 XCore target: Add byval handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187563 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 08:18:55 +00:00
Robert Lytton
98369fb0e7 Xcore target
Fix emitArrayBound() calling OutStreamer.Emit*() multiple times when trying to print a single line

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 07:52:05 +00:00
Reed Kotler
f71698747e Fix some misc. issues with Mips16 fp stubs.
1) They should never be inlined.
2) A naming inconsistency with gcc mips16
3) Stubs should not have the global attribute



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187555 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 02:26:31 +00:00
Eric Christopher
9d45f914f0 Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187554 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 01:38:16 +00:00
Reed Kotler
d49475bebc Add an omitted IsCall=1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187553 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 00:59:06 +00:00
Hans Wennborg
a15d5db7f2 Option parsing: remove non-SUPPORT_ALIASARGS fall-back
The clients of this code have been updated to all support AliasArgs.

This depends on Clang r187538 and lld r187541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 23:28:51 +00:00
Hans Wennborg
9dd8c0cffe Option parsing: add support for alias arguments.
This makes option aliases more powerful by enabling them to
pass along arguments to the option they're aliasing.

For example, if we have a joined option "-foo=", we can now
specify a flag option "-bar" to be an alias of that, with the
argument "baz".

This is especially useful for the cl.exe compatible clang driver,
where many options are aliases. For example, this patch enables
us to alias "/Ox" to "-O3" (-O is a joined option), and "/WX" to
"-Werror" (again, -W is a joined option).

Differential Revision: http://llvm-reviews.chandlerc.com/D1245

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 22:44:41 +00:00
Nadav Rotem
03fb46bed1 80-col
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187535 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 22:17:45 +00:00
Andrew Trick
d3d751804c comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187531 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 21:05:54 +00:00
Kevin Enderby
e38070fc32 Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match.  Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.

rdar://14214063


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 21:05:30 +00:00
Tom Stellard
6b3f6a744a Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:27 +00:00
Tom Stellard
5519dc9de8 Revert "TableGen: Enumerate Schedule Model too."
This reverts commit 2ca1e4a39c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:08 +00:00
Tom Stellard
af2ea2a4fb Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
This reverts commit 3f1de26cb5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:03 +00:00
Vincent Lejeune
26db9ecfac R600: Do not mergevector after a vector reg is used
If we merge vector when a vector is used, it will generate an artificial
antidependency that can prevent 2 tex/vtx instructions to use the same
clause and thus generate extra clauses that reduce performance.

There is no test case as such situation is really hard to predict.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187516 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:32:12 +00:00
Vincent Lejeune
8e37705a73 R600: Avoid more than 4 literals in the same instruction group at scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187515 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:32:07 +00:00
Vincent Lejeune
98ce62780e R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:56 +00:00
Vincent Lejeune
a92f8ee2f3 R600: Don't mix LDS and non-LDS instructions in the same group
There are a lot of restrictions on instruction groups that contain
LDS instructions, so for now we will be conservative and not packetize
anything else with them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:41 +00:00
Vincent Lejeune
3f1de26cb5 R600: Use SchedModel enum for is{Trans,Vector}Only functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:35 +00:00
Vincent Lejeune
2ca1e4a39c TableGen: Enumerate Schedule Model too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187511 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:20 +00:00
Vincent Lejeune
acf7350385 R600: Remove predicated_break inst
We were using two instructions for similar purpose : break and
predicated break. Only predicated_break was emitted and it was
lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP.
This commit simplify the situation by making AMDILCFGStructurizer
emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which
is now removed).

There is no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:14 +00:00
Matt Arsenault
16e4ed5879 Reject bitcasts between address spaces with different sizes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 17:49:08 +00:00
Richard Sandiford
04ded924f3 [SystemZ] Implement isLegalAddressingMode()
The loop optimizers were assuming that scales > 1 were OK.  I think this
is actually a bug in TargetLoweringBase::isLegalAddressingMode(),
since it seems to be trying to reject anything that isn't r+i or r+r,
but it has no default case for scales other than 0, 1 or 2.  Implementing
the hook for z means that z can no longer test any change there though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187497 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 12:58:26 +00:00
Richard Sandiford
15715fb689 [SystemZ] Be more careful about inverting CC masks (conditional loads)
Extend r187495 to conditional loads.  I split this out because the
easiest way seemed to be to force a particular operand order in
SystemZISelDAGToDAG.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 12:38:08 +00:00
Richard Sandiford
6824f127f9 [SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken.  We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities.  For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2.  If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3.  Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.

Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll.  Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.

The patch also makes it easier to reuse CC results from other instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 12:30:20 +00:00
Richard Sandiford
0416e3c599 [SystemZ] Move compare-and-branch generation even later
r187116 moved compare-and-branch generation from the instruction-selection
pass to the peephole optimizer (via optimizeCompare).  It turns out that even
this is a bit too early.  Fused compare-and-branch instructions don't
interact well with predication, where a CC result is needed.  They also
make it harder to reuse the CC side-effects of earlier instructions
(not yet implemented, but the subject of a later patch).

Another problem was that the AnalyzeBranch family of routines weren't
handling compares and branches, so we weren't able to reverse the fused
form in cases where we would reverse a separate branch.  This could have
been fixed by extending AnalyzeBranch, but given the other problems,
I've instead moved the fusing to the long-branch pass, which is also
responsible for the opposite transformation: splitting out-of-range
compares and branches into separate compares and long branches.

I've added a test for the AnalyzeBranch problem.  A test for the
predication problem is included in the next patch, which fixes a bug
in the choice of CC mask.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 12:11:07 +00:00
Elena Demikhovsky
093043ce11 Fixed assertion in Extract128BitVector()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 12:03:08 +00:00
Richard Sandiford
b3f912b510 [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()
r186399 aggressively used the RISBG instruction for immediate ANDs,
both because it can handle some values that AND IMMEDIATE can't,
and because it allows the destination register to be different from
the source.  I realized later while implementing the distinct-ops
support that it would be better to leave the choice up to
convertToThreeAddress() instead.  The AND IMMEDIATE form is shorter
and is less likely to be cracked.

This is a problem for 32-bit ANDs because we assume that all 32-bit
operations will leave the high word untouched, whereas RISBG used in
this way will either clear the high word or copy it from the source
register.  The patch uses the z196 instruction RISBLG for this instead.

This means that z10 will be restricted to NILL, NILH and NILF for
32-bit ANDs, but I think that should be OK for now.  Although we're
using z10 as the base architecture, the optimization work is going
to be focused more on z196 and zEC12.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 11:36:35 +00:00
Elena Demikhovsky
8395251c0a Added INSERT and EXTRACT intructions from AVX-512 ISA.
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 11:35:14 +00:00
Richard Sandiford
f3068d02e5 [SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 11:17:35 +00:00
Richard Trieu
5b62bb0af1 Add parentheses to silence gcc warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 04:07:28 +00:00
Andrew Trick
c408335bf5 Fix register pressure tables on ARM.
The heuristic that merges register pressure sets was bogus for ARM's S/D regs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 03:24:31 +00:00
Andrew Trick
bbf20d4d4a Add tracing to the tblgen register pressure table generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 03:24:28 +00:00
Craig Topper
0c49a9b619 Increment arg_count inside the loop in printInline. Patch by Joe Matarazzo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 03:22:07 +00:00
Craig Topper
418eb3df74 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 02:47:52 +00:00
Andrew Trick
d832d32f57 Fix a severe compile time problem when forming large SCEV expressions.
This fix is very lightweight. The same fix already existed for AddRec
but was missing for NAry expressions.

This is obviously an improvement and I'm unsure how to test compile
time problems.

Patch by Xiaoyi Guo!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187475 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 02:43:40 +00:00
Craig Topper
5bd1b815b3 Remove trailing whitespace and some tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 02:00:15 +00:00
Craig Topper
1a5c55e54d Fixed incorrect disassembly for MOV16o16a when using Intel syntax.
Patch by Richard Mitton.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 01:50:26 +00:00
Eric Christopher
1a54c57cf6 Fix crashing on invalid inline asm with matching constraints.
For a testcase like the following:

 typedef unsigned long uint64_t;

 typedef struct {
   uint64_t lo;
   uint64_t hi;
 } blob128_t;

 void add_128_to_128(const blob128_t *in, blob128_t *res) {
   asm ("PAND %1, %0" : "+Q"(*res) : "Q"(*in));
 }

where we'll fail to allocate the register for the output constraint,
our matching input constraint will not find a register to match,
and could try to search past the end of the current operands array.

On the idea that we'd like to attempt to keep compilation going
to find more errors in the module, change the error cases when
we're visiting inline asm IR to return immediately and avoid
trying to create a node in the DAG. This leaves us with only
a single error message per inline asm instruction, but allows us
to safely keep going in the general case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 01:26:24 +00:00
Akira Hatanaka
782638aa0d [mips] Rename instruction DANDi to ANDi64.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 00:57:41 +00:00
Akira Hatanaka
52b7321a48 [mips] Define instruction itineraries IIArith and IILogic.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 00:55:34 +00:00
Matt Arsenault
1bf0ec4e16 Fix ptr vector inconsistency in CreatePointerCast
One form would accept a vector of pointers, and the other did not.
Make both accept vectors of pointers, and add an assertion
for the number of elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 00:17:33 +00:00
Rafael Espindola
9ce8b2818d Fix windows' implementation of status when a file doesn't exist.
The unix one was returning no_such_file_or_directory, but the windows one
was return success.

Update the one one caller that was depending on the old behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 00:10:25 +00:00
Owen Anderson
605b3427a9 Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187462 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 23:53:17 +00:00
Eric Christopher
b0bee810e7 Reflow this to be easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 22:50:44 +00:00
Eric Christopher
63a5619410 Make these just inline, not static inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 22:35:06 +00:00
Eric Christopher
b9db9cd6a9 Make sure that -gsplit-dwarf isn't passed to the linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187456 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 22:34:30 +00:00