Commit Graph

92416 Commits

Author SHA1 Message Date
Eric Christopher
4d7f2ce938 Make getCompileUnit non-const and return the current DIE if it
happens to be a compile unit. Noticed on inspection and tested
via calling on a newly created compile unit. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 21:33:10 +00:00
Michael Liao
95ab326674 Add 'CHECK-DAG' support
Refer to 'FileCheck.rst'f for details of 'CHECK-DAG'.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181827 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 20:34:12 +00:00
Michael Liao
7efbbd61eb Refactor string checking. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 20:29:52 +00:00
Bill Schmidt
5bbdb19041 Implement the PowerPC system call (sc) instruction.
Instruction added at request of Roman Divacky.  Tested via asm-parser.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 19:35:45 +00:00
Filip Pizlo
13a3cf1928 SectionMemoryManager shouldn't be a JITMemoryManager. Previously, the
EngineBuilder interface required a JITMemoryManager even if it was being used 
to construct an MCJIT. But the MCJIT actually wants a RTDyldMemoryManager. 
Consequently, the SectionMemoryManager, which is meant for MCJIT, derived 
from the JITMemoryManager and then stubbed out a bunch of JITMemoryManager 
methods that weren't relevant to the MCJIT.

This patch fixes the situation: it teaches the EngineBuilder that 
RTDyldMemoryManager is a supertype of JITMemoryManager, and that it's 
appropriate to pass a RTDyldMemoryManager instead of a JITMemoryManager if 
we're using the MCJIT. This allows us to remove the stub methods from 
SectionMemoryManager, and make SectionMemoryManager a direct subtype of 
RTDyldMemoryManager.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 19:29:00 +00:00
Jyotsna Verma
a29a8965e2 Hexagon: Pass to replace tranfer/copy instructions into combine instruction
where possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 18:54:06 +00:00
Eric Christopher
f276c70bb8 Reapply "Subtract isn't commutative, fix this for MMX psub." with
a somewhat randomly chosen cpu that will minimize cpu specific
differences on bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181814 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 18:33:40 +00:00
Eric Christopher
edf0dda528 Temporarily revert "Subtract isn't commutative, fix this for MMX psub."
It's causing failures on the atom bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 18:20:42 +00:00
Rafael Espindola
d1bf52275d Fix __clear_cache declaration.
This fixes the build with gcc in gnu++98 and gnu++11 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181811 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 18:06:14 +00:00
Eric Christopher
304d73c9ee Subtract isn't commutative, fix this for MMX psub.
Patch by Andrea DiBiagio.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181809 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 17:52:05 +00:00
Jakob Stoklund Olesen
bc3db03bf0 Recognize sparc64 as an alias for sparcv9 triples.
Patch by Brad Smith!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 17:47:27 +00:00
Jyotsna Verma
36e1b51438 Hexagon: Add patterns to generate 'combine' instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 17:16:38 +00:00
Jyotsna Verma
91eadc6d69 Hexagon: ArePredicatesComplement should not restrict itself to TFRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 16:36:34 +00:00
Kai Nacke
e4642bc096 Add bitcast to store of personality function.
The personality function is user defined and may have an arbitrary result type.
The code assumes always i8*. This results in an assertion failure if a different
type is used. A bitcast to i8* is added to prevent this failure.

Reviewed by: Renato Golin, Bob Wilson

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 16:30:51 +00:00
Derek Schuff
ed788b6283 Fix ARM FastISel tests, as a first step to enabling ARM FastISel
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on
enabling it for other targets. As a first step I've fixed some of the tests.
Changes to ARM FastISel tests:
- Different triples don't generate the same relocations (especially
  movw/movt versus constant pool loads). Use a regex to allow either.
- Mangling is different. Use a regex to allow either.
- The reserved registers are sometimes different, so registers get
  allocated in a different order. Capture the names only where this
  occurs.
- Add -verify-machineinstrs to some tests where it works. It doesn't
  work everywhere it should yet.
- Add -fast-isel-abort to many tests that didn't have it before.
- Split out the VarArg test from fast-isel-call.ll into its own
  test. This simplifies test setup because of --check-prefix.

Patch by JF Bastien

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 16:26:38 +00:00
Bill Schmidt
ded53bf4dd PPC32: Fix stack collision between FP and CR save areas.
The changes to CR spill handling missed a case for 32-bit PowerPC.
The code in PPCFrameLowering::processFunctionBeforeFrameFinalized()
checks whether CR spill has occurred using a flag in the function
info.  This flag is only set by storeRegToStackSlot and
loadRegFromStackSlot.  spillCalleeSavedRegisters does not call
storeRegToStackSlot, but instead produces MI directly.  Thus we don't
see the CR is spilled when assigning frame offsets, and the CR spill
ends up colliding with some other location (generally the FP slot).

This patch sets the flag in spillCalleeSavedRegisters for PPC32 so
that the CR spill is properly detected and gets its own slot in the
stack frame.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181800 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 16:08:32 +00:00
Jyotsna Verma
21e6ea54ff Hexagon: Test case to check if branch probabilities are properly reflected in
the jump instructions in the form of taken/not-taken hint.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181799 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 15:50:49 +00:00
Jyotsna Verma
9c9bf9a240 Hexagon: Remove dead-code after unconditional return from addPreSched2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 15:33:27 +00:00
Tom Stellard
ec03792245 R600/SI: Add processor type for Hainan asic
Patch by: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 14:42:56 +00:00
Duncan Sands
8305acb200 Get the unittests compiling when building with cmake and the setting
-DLLVM_ENABLE_THREADS=false.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 13:29:16 +00:00
Rafael Espindola
15cf700b41 Declare __clear_cache.
GCC declares __clear_cache in the gnu modes (-std=gnu++98,
-std=gnu++11), but not in the strict modes (-std=c++98, -std=c++11). This patch
declares it and therefore fixes the build when using one of the strict modes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181785 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 13:02:37 +00:00
Richard Sandiford
c3b20c260e [SystemZ] Add disassembler support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 10:17:52 +00:00
Michel Danzer
5096dc74ae R600/SI: Add lit test coverage for the remaining patterns added recently
Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 09:53:30 +00:00
Richard Sandiford
847cb575a1 [SystemZ] Add extra testscases for r181773
Forgot to svn add these...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 09:49:11 +00:00
Richard Sandiford
b594c4c873 [SystemZ] Rework handling of constant PC-relative operands
The GNU assembler treats things like:

        brasl   %r14, 100

in the same way as:

        brasl   %r14, .+100

rather than as a branch to absolute address 100.  We implemented this in
LLVM by creating an immediate operand rather than the usual expr operand,
and by handling immediate operands specially in the code emitter.
This was undesirable for (at least) three reasons:

- the specialness of immediate operands was exposed to the backend MC code,
  rather than being limited to the assembler parser.

- in disassembly, an immediate operand really is an absolute address.
  (Note that this means reassembling printed disassembly can't recreate
  the original code.)

- it would interfere with any assembly manipulation that we might
  try in future.  E.g. operations like branch shortening can change
  the relative position of instructions, but any code that updates
  sym+offset addresses wouldn't update an immediate "100" operand
  in the same way as an explicit ".+100" operand.

This patch changes the implementation so that the assembler creates
a "." label for immediate PC-relative operands, so that the operand
to the MCInst is always the absolute address.  The patch also adds
some error checking of the offset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 09:47:26 +00:00
Richard Sandiford
58b854d7e9 [SystemZ] Remove bogus isAsmParserOnly
Marking instructions as isAsmParserOnly stops them from being disassembled.
However, in cases where separate asm and codegen versions exist, we actually
want to disassemble to the asm ones.

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 09:38:07 +00:00
Richard Sandiford
f917bc0406 [SystemZ] Match operands to fields by name rather than by order
The SystemZ port currently relies on the order of the instruction operands
matching the order of the instruction field lists.  This isn't desirable
for disassembly, where the two are matched only by name.  E.g. the R1 and R2
fields of an RR instruction should have corresponding R1 and R2 operands.

The main complication is that addresses are compound operands,
and as far as I know there is no mechanism to allow individual
suboperands to be selected by name in "let Inst{...} = ..." assignments.
Luckily it doesn't really matter though.  The SystemZ instruction
encoding groups all address fields together in a predictable order,
so it's just as valid to see the entire compound address operand as
a single field.  That's the approach taken in this patch.

Matching by name in turn means that the operands to COPY SIGN and
CONVERT TO FIXED instructions can be given in natural order.
(It was easier to do this at the same time as the rename,
since otherwise the intermediate step was too confusing.)

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 09:36:44 +00:00
Richard Sandiford
055ac429cc [SystemZ] Match operands to fields by name rather than by order
The SystemZ port currently relies on the order of the instruction operands
matching the order of the instruction field lists.  This isn't desirable
for disassembly, where the two are matched only by name.  E.g. the R1 and R2
fields of an RR instruction should have corresponding R1 and R2 operands.

The main complication is that addresses are compound operands,
and as far as I know there is no mechanism to allow individual
suboperands to be selected by name in "let Inst{...} = ..." assignments.
Luckily it doesn't really matter though.  The SystemZ instruction
encoding groups all address fields together in a predictable order,
so it's just as valid to see the entire compound address operand as
a single field.  That's the approach taken in this patch.

Matching by name in turn means that the operands to COPY SIGN and
CONVERT TO FIXED instructions can be given in natural order.
(It was easier to do this at the same time as the rename,
since otherwise the intermediate step was too confusing.)

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 09:28:21 +00:00
Michael Gottesman
cbe5f4c5d7 Removed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 06:40:10 +00:00
Reed Kotler
0b95db8f26 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 06:00:01 +00:00
Reed Kotler
5427aa88d5 Removed an unnamed namespace and forgot to make two of the functions inside
"static".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 02:13:45 +00:00
Reed Kotler
eafa96485a This is the first of three patches which creates stubs used for
Mips16/32 floating point interoperability.

When Mips16 code calls external functions that would normally have some
of its parameters or return values passed in floating point registers,
it needs (Mips32) helper functions to do this because while in Mips16 mode
there is no ability to access the floating point registers.

In Pic mode, this is done with a set of predefined functions in libc.
This case is already handled in llvm for Mips16.

In static relocation mode, for efficiency reasons, the compiler generates
stubs that the linker will use if it turns out that the external function
is a Mips32 function. (If it's Mips16, then it does not need the helper
stubs).

These stubs are identically named and the linker knows about these tricks
and will not create multiple copies and will delete them if they are not
needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 02:00:24 +00:00
Akira Hatanaka
dd29df06fa StackColoring: don't clear an instruction's mem operand if the underlying
object is a PseudoSourceValue and PseudoSourceValue::isConstant returns true (i.e.,
points to memory that has a constant value).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 01:42:44 +00:00
David Blaikie
17a692e7f1 Assert that DIEEntries are constructed with non-null DIEs
This just brings a crash a little further forward from DWARF emission to
DIE construction to make errors easier to diagnose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181748 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 00:35:19 +00:00
Arnold Schwaighofer
123f18bcb9 LoopVectorize: Handle loops with multiple forward inductions
We used to give up if we saw two integer inductions. After this patch, we base
further induction variables on the chosen one like we do in the reverse
induction and pointer induction case.

Fixes PR15720.

radar://13851975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 00:21:18 +00:00
Michael Gottesman
dba53a8c9d [objc-arc-opts] Added debug statements when we set and unset whether a pointer is known positive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14 00:08:09 +00:00
Michael Gottesman
acfb3584c5 [objc-arc-opts] In the presense of an alloca unconditionally remove RR pairs if and only if we are both KnownSafeBU/KnownSafeTD rather than just either or.
In the presense of a block being initialized, the frontend will emit the
objc_retain on the original pointer and the release on the pointer loaded from
the alloca. The optimizer will through the provenance analysis realize that the
two are related (albiet different), but since we only require KnownSafe in one
direction, will match the inner retain on the original pointer with the guard
release on the original pointer. This is fixed by ensuring that in the presense
of allocas we only unconditionally remove pointers if both our retain and our
release are KnownSafe (i.e. we are KnownSafe in both directions) since we must
deal with the possibility that the frontend will emit what (to the optimizer)
appears to be unbalanced retain/releases.

An example of the miscompile is:

  %A = alloca
  retain(%x)
  retain(%x) <--- Inner Retain
  store %x, %A
  %y = load %A
  ... DO STUFF ...
  release(%y)
  call void @use(%x)
  release(%x) <--- Guarding Release

getting optimized to:

  %A = alloca
  retain(%x)
  store %x, %A
  %y = load %A
  ... DO STUFF ...
  release(%y)
  call void @use(%x)

rdar://13750319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 23:49:42 +00:00
Matt Beaumont-Gay
9b5e6c0943 Move a couple more statistics inside '#ifndef NDEBUG'.
Suppresses an unused-variable warning in -Asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 21:10:49 +00:00
Jack Carter
f4a1377322 Mips assembler: Assembler macro ADDIU $rs,imm
This patch adds alias for addiu instruction which enables following syntax:

    addiu $rs,imm

The macro is translated as:

    addiu $rs,$rs,imm


Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 20:26:46 +00:00
Michael Gottesman
774a8cf2f5 [objc-arc-opts] Add comment to BBState making it clear that get{TopDown,BottomUp}PtrState will create a new PtrState object if it does not find a PtrState for Arg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181726 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 19:40:39 +00:00
Bill Schmidt
59b078fc56 Fix goofy commentary in PPCTargetObjectFile.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 19:40:36 +00:00
Bill Schmidt
240b9b6078 PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.
This fixes warning messages observed in the oggenc application test in
projects/test-suite.  Special handling is needed for the 64-bit
PowerPC SVR4 ABI when a constant is initialized with a pointer to a
function in a shared library.  Because a function address is
implemented as the address of a function descriptor, the use of copy
relocations can lead to problems with initialization.  GNU ld
therefore replaces copy relocations with dynamic relocations to be
resolved by the dynamic linker.  This means the constant cannot reside
in the read-only data section, but instead belongs in .data.rel.ro,
which is designed for constants containing dynamic relocations.

The implementation creates a class PPC64LinuxTargetObjectFile
inheriting from TargetLoweringObjectFileELF, which behaves like its
parent except to place constants of this sort into .data.rel.ro.

The test case is reduced from the oggenc application.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 19:34:37 +00:00
Bob Wilson
a753ff72b2 Remove redundant variable introduced by r181682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 19:02:31 +00:00
Michael Gottesman
fa709768b9 [objc-arc] Move the before optimization statistics gathering phase out of OptimizeIndividualCalls.
This makes the statistics gathering completely independent of the actual
optimization occuring, preventing any sort of bleeding over from occuring.

Additionally, it simplifies a switch statement in the non-statistic gathering case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181719 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 18:29:07 +00:00
Akira Hatanaka
42f562a169 [mips] Add option -mno-ldc1-sdc1.
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 18:23:35 +00:00
Shuxin Yang
4b6b53b0ce Fix a bug that APFloat::fusedMultiplyAdd() mistakenly evaluate "14.5f * -14.5f + 225.0f" to 225.0f.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 18:03:12 +00:00
Akira Hatanaka
151687cb8c [mips] Define a helper function which creates an instruction with the same
operands as the prototype instruction but with a different opcode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181714 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 17:57:42 +00:00
Akira Hatanaka
6daba28683 [mips] Rename functions. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 17:43:19 +00:00
Rafael Espindola
6eb70ac034 Remove unused fields and arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 14:34:48 +00:00
Mihai Popa
f86e436fb9 The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 14:10:04 +00:00