Craig Topper
54f952afac
Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144989 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 09:02:40 +00:00
Craig Topper
3113384a34
Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 07:33:10 +00:00
Craig Topper
1666cb6d63
Extend VPBLENDVB and VPSIGN lowering to work for AVX2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 07:07:26 +00:00
Craig Topper
787a88ff18
Remove some unnecessary filtering checks from X86 disassembler table build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 05:48:20 +00:00
Craig Topper
60d9a9206e
Remove unused parameters from the AVX maskmov classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144985 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 04:49:22 +00:00
Andrew Trick
5865a8dfde
Fix a corner case in updating LoopInfo after fully unrolling an outer loop.
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The loop tree's inclusive block lists are painful and expensive to
update. (I have no idea why they're inclusive). The design was
supposed to handle this case but the implementation missed it and my
unit tests weren't thorough enough.
Fixes PR11335: loop unroll update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 03:42:41 +00:00
Nadav Rotem
cbbe33fde4
Add AVX2 vpbroadcast support
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144967 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 02:49:55 +00:00
Kostya Serebryany
5a3a9c9371
[asan] workaround for reg alloc bug 11395: don't instrument functions with large chunks of inline assembler
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 01:41:06 +00:00
Chad Rosier
424fe0e422
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 01:17:34 +00:00
Devang Patel
ce35d8b5a1
DISubrange supports unsigned lower/upper array bounds, so let's not fake it in the end while emitting DWARF. If a FE needs to encode signed lower/upper array bounds then we need to extend DISubrange or ad DISignedSubrange.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:43:15 +00:00
Kostya Serebryany
2e7fb2f736
quick fix: remove GlobalVariable::GlobalVariable mistakenly commited at r144933. For some reason this compiles on linux
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:37:53 +00:00
Andrew Trick
4f3052403c
Fix an overly general check in SimplifyIndvar to handle useless phi cycles.
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The right way to check for a binary operation is
cast<BinaryOperator>. The original check: cast<Instruction> &&
numOperands() == 2 would match phi "instructions", leading to an
infinite loop in extreme corner case: a useless phi with operands
[self, constant] that prior optimization passes failed to remove,
being used in the loop by another useless phi, in turn being used by an
lshr or udiv.
Fixes PR11350: runaway iteration assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:36:35 +00:00
Kostya Serebryany
7cf2a04361
fall back to explicit list of allowed linkages when instrumenting globals in asan; add a test check that asan does not touch linkonce_odr
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144933 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:14:59 +00:00
Ted Kremenek
f249449539
Fix bug in RefCountedBase/RefCountedBaseVPTR where the reference count was accidentally copied as part of the copy constructor. This could result in objects getting leaked because there reference count was too high.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144931 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:02:14 +00:00
Chad Rosier
944d82ba06
Add TODO comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144920 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 21:46:13 +00:00
Craig Topper
d90a191685
Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:49:38 +00:00
Chad Rosier
2fb82ce75d
Dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:24:49 +00:00
Chad Rosier
478b06c980
When fast iseling a GEP, accumulate the offset rather than emitting a series of
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ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD. Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to
coalesce ADDs.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:15:58 +00:00
Craig Topper
ec43d1f553
Remove seemingly unnecessary duplicate VROUND definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:04:00 +00:00
Chris Lattner
c78daaf0da
x86/windows issues fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144878 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:42:23 +00:00
Eli Friedman
9d434dbff3
Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
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names for fwrite and fputs.
Fixes <rdar://problem/9815881>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:27:36 +00:00
Daniel Dunbar
d5889d8c7f
llvm-build: Attempt to work around a CMake Makefile generator bug that doesn't
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properly quote strings when writing the CMakeFiles/Makefile.cmake output file
(which lists the dependencies). This shows up when using CMake + MSYS Makefile
generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:19:53 +00:00
Chad Rosier
3bdb3c9b51
Don't unconditionally set the kill flag.
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rdar://10456186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:16:53 +00:00
Eli Friedman
d224c7879a
Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 00:21:52 +00:00
Daniel Dunbar
708276d6e4
build/make/test: Get rid of unused BUGPOINT_TOPTS variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 23:56:03 +00:00
Eli Friedman
4db4addcd4
Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 23:50:22 +00:00
Michael J. Spencer
11ba26db13
Object/COFF: Support common symbols.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 23:36:12 +00:00
Jim Grosbach
9b1671bae7
Remove obsolete test.
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The PLD encoding is checked via the .s file now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:50:38 +00:00
Jim Grosbach
2abba8496c
Generalize the fixup info for ARM mode.
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We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:48:37 +00:00
Jim Grosbach
47a906ac23
Update test for r144842.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:46:27 +00:00
Akira Hatanaka
620db8947a
Lower 64-bit constant pool node.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:44:38 +00:00
Akira Hatanaka
9b944a8da2
Lower 64-bit block address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:42:10 +00:00
Jim Grosbach
b84acd2468
Fix encoding of NOP used for padding in ARM mode .align.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:40:25 +00:00
Akira Hatanaka
74c76347d3
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
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nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:39:56 +00:00
Akira Hatanaka
4fd40b3604
64-bit jump register instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:36:01 +00:00
Evan Cheng
2b89498979
Another missing X86ISD::MOVLPD pattern. rdar://10450317
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144839 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:24:44 +00:00
Jim Grosbach
40a86ee20f
ARM assembly parsing for shifted register operands for MOV instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:50:05 +00:00
Jim Grosbach
efed3d1f58
Clean up debug printing of ARM shifted operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:46:50 +00:00
Chad Rosier
053e69ad57
Add fast-isel stats to determine who's doing all the work, the
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target-independent selector or the target-specific selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:05:28 +00:00
Chad Rosier
f91488cc10
Fix the stats collection for fast-isel. The failed count was only accounting
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for a single miss and not all predecessor instructions that get selected by
the selection DAG instruction selector. This is still not exact (e.g., over
states misses when folded/dead instructions are present), but it is a step in
the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:02:08 +00:00
Chandler Carruth
2929de422e
There are already problems with building LLVM under VS2005, and it's
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quite old now. Update the documentation to reflect this, and direct
people to use VS2008 or newer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:52:13 +00:00
Jim Grosbach
b598b04409
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:12:24 +00:00
Jim Grosbach
48b368bcd5
ARM assembly parsing for RRX mnemonic.
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rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:05:59 +00:00
Pete Cooper
cd75e44173
Added missing comment about new custom lowering of DEC64
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:03:23 +00:00
Evan Cheng
c3aa7c5c5a
Disable expensive two-address optimizations at -O0. rdar://10453055
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:44:48 +00:00
Chad Rosier
508a1f4db1
Check to make sure we can select the instruction before trying to put the
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operands into a register. Otherwise, we may materialize dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:39:44 +00:00
Evan Cheng
14117c4477
Disable the assertion again. Looks like fastisel is still generating bad kill markers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144804 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:32:14 +00:00
Jim Grosbach
23f220705a
ARM mode aliases for bitwise instructions w/ register operands.
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rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:31:45 +00:00
Bob Wilson
d0405aaabc
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 17:09:59 +00:00
NAKAMURA Takumi
5c283e98c9
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 09:18:28 +00:00