Arnold Schwaighofer
5be946b486
ARM sched model: Add integer VFP/SIMD instructions on Swift
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Reapply 183269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183441 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 20:26:18 +00:00
Jakub Staszak
3facc43ff6
Re-apply "Use IRBuilder instead of ConstantInt methods." with the fixed issues.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183439 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 20:18:46 +00:00
Arnold Schwaighofer
d9445b6221
ARM sched model: Add integer load/store instructions on Swift
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Reapply 183268.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 20:11:56 +00:00
Arnold Schwaighofer
67c2056e00
ARM sched model: Add integer arithmetic instructions on Swift
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Reapply 183267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183436 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 19:49:46 +00:00
Arnold Schwaighofer
d8f8c35f4d
ARM sched model: Cortex A9 - More InstRW sched resources
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Add more InstRW mappings.
Reapply 183266.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183435 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 19:30:21 +00:00
Arnold Schwaighofer
f1f6dcefa8
ARM sched model: Add branch thumb instructions
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Reapply 183265.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 18:51:01 +00:00
Arnold Schwaighofer
a6db677197
ARM sched model: Add branch thumb2 instructions
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Reapply 183264.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183430 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 18:42:09 +00:00
Arnold Schwaighofer
87aab6dc96
ARM sched model: Add branch instructions
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Reapply 183263.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 18:21:13 +00:00
Arnold Schwaighofer
3ba4778c95
ARM sched model: Add preload thumb2 instructions
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Reapply 183262.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 18:06:30 +00:00
Arnold Schwaighofer
e022a6b0f4
ARM sched model: Add preload instructions
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Reapply 183261.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 17:26:12 +00:00
Kevin Enderby
54154f3bf1
Teach llvm-objdump with the -macho parser how to use the data in code table
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from the LC_DATA_IN_CODE load command. And when disassembling print
the data in code formatted for the kind of data it and not disassemble those
bytes.
I added the format specific functionality to the derived class MachOObjectFile
since these tables only appears in Mach-O object files. This is my first
attempt to modify the libObject stuff so if folks have better suggestions
how to fit this in or suggestions on the implementation please let me know.
rdar://11791371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 17:20:50 +00:00
Arnold Schwaighofer
f2988a0084
ARM sched model: Add more ALU and CMP thumb instructions
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Reapply of 183260.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 17:03:13 +00:00
Rafael Espindola
7de80e04d9
Revert "Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit."
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This reverts commit 183328. It caused pr16244 and broke the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183422 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 17:03:05 +00:00
Arnold Schwaighofer
826de688b0
ARM sched model: Add more ALU and CMP thumb2 instructions
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Reapply of 183259.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 16:35:25 +00:00
Vincent Lejeune
5f035d048e
R600: Remove leftover code in R600MachineScheduler.cpp
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Spotted by Benjamin Kramer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 14:18:29 +00:00
Rafael Espindola
e3a0e7f29d
Print symbol names in relocations when dumping COFF as YAML.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 13:06:17 +00:00
Bill Wendling
2ed7659b88
Cast to the correct type. Pointer, not reference.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 05:39:29 +00:00
NAKAMURA Takumi
0ac857462f
R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized]
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FIXME: Is it false alarm?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183371 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:12 +00:00
NAKAMURA Takumi
7b6d32a361
R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183370 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:06 +00:00
NAKAMURA Takumi
3ebcf388cd
Trailing linefeed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 02:15:00 +00:00
Bill Wendling
b88cef5a16
Cast to the proper type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 01:04:21 +00:00
Jakub Staszak
c6e2ab3a57
Remove unneeded cast<>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:49:57 +00:00
Bill Wendling
6a2e7ac0b6
Cache the TargetLowering info object as a pointer.
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Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:43:09 +00:00
Jakub Staszak
f2d03d74ff
Use IRBuilder instead of ConstantInt methods.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:37:23 +00:00
Bill Wendling
384ceb8446
Don't cache the TargetLoweringInfo object inside of the FunctionLowering object.
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The TargetLoweringInfo object is owned by the TargetMachine. In the future, the
TargetMachine object may change, which may also change the TargetLoweringInfo
object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:11:39 +00:00
Sean Silva
4370ddb8b8
Add writeAsHex(raw_ostream &) method to BinaryRef.
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This hides the implementation. A future commit will remove the
error-prone getHex() and getBinary() methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 23:47:23 +00:00
Tom Stellard
c170230b3a
R600: Replace predicate loop with predicate function
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183351 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 23:39:50 +00:00
Sean Silva
6acc982e74
Rename BinaryRef::isBinary to more descriptive DataIsHexString.
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And add a doxygen comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183350 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 23:32:31 +00:00
Bill Wendling
08368387a4
Add space to assert message.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 23:13:26 +00:00
Sean Silva
639adc59f8
Add writeAsBinary(raw_ostream &) method to BinaryRef.
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Previously, yaml2coff.cpp had a writeHexData static helper function to
do this, but it is generally useful functionality.
Also, validate hex strings up-front to avoid running having to handle
errors "deep inside" the yaml2obj code (it also gives better diagnostics
than it used to).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183345 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 22:59:00 +00:00
Vincent Lejeune
f3d6e32c09
R600: Add a pass that merge Vector Register
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Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 21:38:04 +00:00
Vincent Lejeune
512119770e
R600: Schedule copy from phys register at beginning of block
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It allows regalloc pass to remove them by trivially assigning associated reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 20:27:35 +00:00
Akira Hatanaka
8270e68c56
[mips] brcond + setgt/setugt instruction selection patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 19:49:55 +00:00
Jakub Staszak
cc81b38c4c
Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 18:27:02 +00:00
Michael Liao
9a508ef64a
[PATCH] Fix VGATHER* operand constraints
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Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."
---
[1] http://software.intel.com/sites/default/files/319433-014.pdf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 18:12:26 +00:00
Arnold Schwaighofer
31588f3005
ARM sched model: Add more ALU and CMP instructions
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Reapply of 183258.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183321 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 16:36:51 +00:00
Arnold Schwaighofer
c82157378e
ARM sched model: Add divsion, loads, branches, vfp cvt
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Add some generic SchedWrites and assign resources for Swift and Cortex A9.
Reapply of r183257. (Removed empty InstRW for division on swift)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 16:06:11 +00:00
Arnold Schwaighofer
d87bd5627e
ARMInstrInfo: Improve isSwiftFastImmShift
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An instruction with less than 3 inputs is trivially a fast immediate shift.
Reapply of 183256, should not have caused the tablegen segfault on linux either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 14:59:36 +00:00
Mihai Popa
2248cf5906
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
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According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 13:23:51 +00:00
David Blaikie
032d62487c
PR15662: Optimized debug info produces out of order function parameters
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When a function is inlined we lazily construct the variables
representing the function's parameters. After that, we add any remaining
unused parameters.
If the function doesn't use all the parameters, or uses them out of
order, then the DWARF would produce them in that order, producing a
parameter order that doesn't match the source.
This fix causes us to always keep the arg variables at the start of the
variable list & in the original order from the source.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 05:39:59 +00:00
Tom Stellard
ad7ecc65b1
R600: Make sure to schedule AR register uses and defs in the same clause
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Reviewed-by: vljn at ovi.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 03:43:06 +00:00
Rafael Espindola
23a22cdedd
Don't print default values for NumberOfAuxSymbols and AuxiliaryData.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 03:20:13 +00:00
Rafael Espindola
0962b1683f
Handle (at least don't crash on) relocations with no symbols.
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Should fix the MCJIT tests on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 02:55:01 +00:00
Rafael Espindola
5fd5fe0f7b
Move BinaryRef to a new include/llvm/Object/YAML.h file.
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It will be used for ELF dumping too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183287 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 02:32:26 +00:00
Rafael Espindola
6afb65c2b7
Revert "R600: Add a pass that merge Vector Register"
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This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:48:30 +00:00
Rafael Espindola
6c1202c459
Handle relocations that don't point to symbols.
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In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:33:53 +00:00
Vincent Lejeune
bbbdba891b
R600: Add a pass that merge Vector Register
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d
R600: Const/Neg/Abs can be folded to dot4
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:15 +00:00
Evan Cheng
00ed010d9e
Cortex-R5 can issue Thumb2 integer division instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:52:09 +00:00
Arnold Schwaighofer
8a227084a5
Revert series of sched model patches until I figure out what is going on.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:35:17 +00:00