Commit Graph

24753 Commits

Author SHA1 Message Date
Dmitri Gribenko
5c332dbd30 Add ArrayRef constructor from None, and do the cleanups that this constructor enables
Patch by Robert Wilhelm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 00:40:33 +00:00
Nadav Rotem
76be9bf67e whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 23:27:32 +00:00
Nadav Rotem
0fb6523eae Fix an odd comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 23:24:56 +00:00
Tim Northover
7428539a1c AArch64: enable MCJIT and tests now that everything passes.
This removes dire warnings about AArch64 being unsupported and enables
the tests when appropriate on this platform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:14:22 +00:00
Tim Northover
85829bb98a AArch64: implement first relocation required for MCJIT
R_AARCH64_PCREL32 is present in even trivial .eh_frame sections and so
is required to compile any function without the "nounwind" attribute.

This change implements very basic infrastructure in the RuntimeDyldELF
file and allows (for example) the test-shift.ll MCJIT test to pass
on AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:13:59 +00:00
Tim Northover
bd121f5b3a Build system changes to enable MCJIT on AArch64
These changes just allow AArch64 to take part in the MCJIT world when
built correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:13:52 +00:00
Richard Osborne
7153a30610 Fix buildbot failure on 64 bit linux due to std::max() having different
operand types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:41:01 +00:00
Richard Osborne
43c7abee14 [XCore] Remove unused operand type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181127 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:30:05 +00:00
Richard Osborne
6ffbf6ea8f [XCore] Make use of the target independent global address offset folding.
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:24:33 +00:00
Richard Osborne
40827bc716 [XCore] Simplify code that checks for an aligned base plus a constant.
The code now makes use of ComputeMaskedBits,
SelectionDAG::isBaseWithConstantOffset and TargetLowering::isGAPlusOffset
where appropriate reducing the amount of logic needed in XCoreISelLowering.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:17:10 +00:00
Richard Osborne
597432fbe5 [XCore] Move lowering of thread local storage to a separate pass.
Thread local storage is not supported by the XMOS linker so we handle
thread local variables by lowering the variable to an array of n elements
(where n is the number of hardware threads per core, currently 8
for all XMOS devices) indexed by the the current thread ID.

Previously this lowering was spread across the XCoreISelLowering and the
XCoreAsmPrinter classes. Moving this to a separate pass should be much
cleaner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:01:55 +00:00
Tim Northover
effc16bb49 AArch64: assert code model is small for TLS accesses
Supporting TLS in the large memory model is rather difficult at the
moment, so make sure no-one gets into difficulties by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:11 +00:00
Tim Northover
79c1c092df AArch64: support literal pool access in large memory model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:07 +00:00
Tim Northover
cd1b09b25b AArch64: support large code model for jump-tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:00 +00:00
Tim Northover
b2efdde06c AArch64: implement support for blockaddress in large code model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:53:53 +00:00
Tim Northover
45db92038b AArch64: implement large code model access to global variables.
The MOVZ/MOVK instruction sequence may not be the most efficient (a
literal-pool load could be better) but adding that would require
reinstating the ConstantIslands pass.

For now the sequence is correct, and that's enough. Beware, as of
commit GNU ld does not appear to support the relocations needed for
this. Its primary purpose (for now) will be to support JITed code,
since in that case there is no guarantee of where your code will end
up in memory relative to external symbols it references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:53:46 +00:00
Richard Osborne
0c66f30325 [XCore] Use static relocation model by default.
This allows us to get get rid of a hack in XCoreTargetObjectFile where the
the DataRel* sections were overridden.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:40:58 +00:00
Krzysztof Parzyszek
cc420a0911 Use consistent function names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 01:30:49 +00:00
Amara Emerson
1aef163a68 Revert r181009.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181079 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 23:57:17 +00:00
Reed Kotler
2bb955a693 Remove some uneeded pseudos in the presence of the naked function attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 23:17:24 +00:00
Ulrich Weigand
fcdfd5a7ff [PowerPC] Avoid using '$' in generated assembler code
PowerPC assemblers are supposed to support a stand-alone '$' symbol
as an alternative of '.' to refer to the current PC.  This does not
work in the LLVM assembler parser yet.

To avoid bootstrap failures when using the LLVM assembler as system
assembler, this patch modifies the assembler source code generated
by LLVM to avoid using '$' (and simply use '.' instead).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:53:04 +00:00
Ulrich Weigand
8e4ba8f7b1 [PowerPC] Add some Book II instructions to AsmParser
This patch adds a couple of Book II instructions (isync, icbi) to the
PowerPC assembler parser.  These are needed when bootstrapping clang
with the integrated assembler forced on, because they are used in
inline asm statements in the code base.

The test case adds the full list of Book II storage control instructions,
including associated extended mnemonics.  Again, those that are not yet
supported as marked as FIXME.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:51:09 +00:00
Ulrich Weigand
16adfdb2e6 [PowerPC] Support extended mnemonics in AsmParser
This patch adds infrastructure to support extended mnemonics in the
PowerPC assembler parser.  It adds support specifically for those
extended mnemonics that LLVM will itself generate.

The test case lists *all* extended mnemonics according to the
PowerPC ISA v2.06 Book I, but marks those not yet supported
as FIXME.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:50:27 +00:00
Ulrich Weigand
5e220753ff [PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.

The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux.  The supported syntax is
intended to be compatible with the GNU assembler.

The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.

Instruction operands will be checked for validity and errors
generated.  (Error handling in general could still be improved.)

The patch adds a number of test cases to verify instruction
and operand encodings.  The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector. 
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.

A number of follow-on check-ins will add extra features.  When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:49:39 +00:00
Akira Hatanaka
a2b2200ff8 [mips] Split the DSP control register and define one register for each field of
its fields.

This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 18:37:49 +00:00
Tom Stellard
19301d5d12 R600: Expand vector or, shl, srl, and xor nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:31 +00:00
Tom Stellard
8b1c60c151 R600: BFI_INT is a vector-only instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:24 +00:00
Tom Stellard
83f0a5a5e8 R600: Add pattern for SHA-256 Ma function
This can be optimized using the BFI_INT instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:20 +00:00
Tom Stellard
218b20a81e R600: Clean up comments in Processors.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:14 +00:00
Amara Emerson
5d446e61d9 Add support for reading ARM ELF build attributes.
Build attribute sections can now be read if they exist via ELFObjectFile, and
the llvm-readobj tool has been extended with an option to dump this information
if requested. Regression tests are also included which exercise these features.

Also update the docs with a fixed ARM ABI link and a new link to the Addenda
which provides the build attributes specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 11:36:35 +00:00
Benjamin Kramer
b9548d8ee3 X86: Add target description for btver2; make autodetection logic aware of AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 10:20:08 +00:00
Aaron Ballman
3ff641f222 Unbreaking the non-x86 build bots by protecting the AVX test code properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 02:52:21 +00:00
Aaron Ballman
f57563b61b Correctly testing for AVX support in x86 based off code from Hosts.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180991 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 02:39:21 +00:00
Reid Kleckner
aa35a56975 Fix missing include in Hexagon code for Release+Asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 00:54:56 +00:00
John McCall
26f3bb997f In MC asm parsing, account for the possibility of whitespace within
the "identifier" parsed by the frontend callback by skipping forward
until we've consumed a token that ends at the point dictated by the
callback.

In addition, inform the callback when it's parsing an unevaluated
operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one
(e.g. mov eax, [A::x]).

This commit depends on a clang commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180978 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 00:15:41 +00:00
Akira Hatanaka
99ad6ac65e [mips] Handle reading, writing or copying of ccond field of DSP control
register.

- Define pseudo instructions which store or load ccond field of the DSP
  control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 23:07:05 +00:00
Jyotsna Verma
d4f8a6b9e9 reverting r180953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 22:10:59 +00:00
Vincent Lejeune
5ed88013e8 R600: Signed literals are 64bits wide
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180960 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:53:03 +00:00
Vincent Lejeune
152ebee8f3 R600: If previous bundle is dot4, PV valid chan is always X
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:55 +00:00
Vincent Lejeune
9e1808733e R600: Improve asmPrint of ALU clause
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:40 +00:00
Vincent Lejeune
92f24d403f R600: Prettier asmPrint of Alu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:30 +00:00
Jyotsna Verma
8a3f50038f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:21:57 +00:00
Pranav Bhandarkar
02d937d864 Hexagon - Add peephole optimizations for zero extends.
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 20:22:51 +00:00
Richard Sandiford
e2e80cbdcf [mips] Fix the head Mips16RegisterInfo.cpp comment
...aka a test commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180936 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 18:28:03 +00:00
Jyotsna Verma
f945d09d53 Hexagon: Honor __builtin_expect by using branch probabilities.
* lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
  Given a jump opcode return the right pred.new jump opcode with
  a taken vs not-taken hint based on branch probabilities provided
  by the target independent module.
  * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
  * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
  Enhance existing function use branch probabilities like
  HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180923 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:39:30 +00:00
Tom Stellard
399880527d R600: Use new tablegen syntax for patterns
All but two patterns have been converted to the new syntax.  The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180922 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:30:12 +00:00
Tom Stellard
5ed242c240 R600/SI: remove nonsense select pattern
Fortunately this pattern never matched, otherwise
we would have generated incorrect code.

Signed-off-by: Christian K??nig <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180921 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:30:07 +00:00
Michael Liao
299eb2e6e1 80-col fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180915 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 09:22:04 +00:00
Michael Liao
db7da200a4 Avoid duplicating logic on frame register selecting when lowering eh_return
No functionality change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180914 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 09:18:38 +00:00
Michael Liao
b9cca13063 Avoid duplicating logic on frame register selecting when lowering frameaddr
No functionality change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180912 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 08:21:56 +00:00