Commit Graph

63534 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
64baddc0f2 Some small clean-up: use of pseudo instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:55:18 +00:00
Johnny Chen
1adc40cac3 Cleaned up the for-disassembly-only entries in the arm instruction table so that
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:46:17 +00:00
Jakob Stoklund Olesen
fff2c4726b Also recompute HasPHIKill flags in LiveInterval::RenumberValues.
If a phi-def value were removed from the interval, the phi-kill flags are no
longer valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:38:03 +00:00
Evan Cheng
719510a178 Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:30:05 +00:00
Bruno Cardoso Lopes
642eb02045 - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:20:53 +00:00
Jakob Stoklund Olesen
1b2932024f Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:01:23 +00:00
Jakob Stoklund Olesen
e1f543fbb3 Clean up debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 18:50:55 +00:00
Bruno Cardoso Lopes
6da9cee0f1 Define AVX 128-bit pattern versions of SET0PS/PD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 18:20:59 +00:00
Bob Wilson
a825a634be Add a test for llvm-gcc svn 110632.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 17:31:41 +00:00
Jakob Stoklund Olesen
f1b05f2b0e Implement single block splitting.
Before spilling a live range, we split it into a separate range for each basic
block where it is used. That way we only get one reload per basic block if the
new smaller ranges can allocate to a register.

This type of splitting is already present in the standard spiller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 17:07:14 +00:00
Dan Gohman
727356fc7d Optimize ScalarEvolution::getAddExpr's operand factoring code by
having it finish processing all of the muliply operands before
starting the whole getAddExpr process over again, instead of
immediately after the first simplification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 15:00:23 +00:00
Dan Gohman
918e76b8b5 Hoist some loop-invariant code out of a hot loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 14:52:55 +00:00
Dan Gohman
dc7692b1ad Optimize ScalarEvolution::getAddExpr's duplicate operand detection
by having it finish processing the whole operand list before
starting the whole getAddExpr process over again, instead of
immediately after the first duplicate is found.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 14:46:54 +00:00
Duncan Sands
335db22392 Add a 'normalize' method to the Triple class, which takes a mucked up
target triple and straightens it out.  This does less than gcc's script
config.sub, for example it turns i386-mingw32 into i386--mingw32 not
i386-pc-mingw32, but it does a decent job of turning funky triples into
something that the rest of the Triple class can understand.  The plan
is to use this to canonicalize triple's when they are first provided
by users, and have the rest of LLVM only deal with canonical triples.
Once this is done the special case workarounds in the Triple constructor
can be removed, making the class more regular and easier to use.  The
comments and unittests for the Triple class are already adjusted in this
patch appropriately for this brave new world of increased uniformity.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110909 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 11:31:39 +00:00
Eric Christopher
7486278900 Temporarily revert 110737 and 110734, they were causing failures
in an external testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 07:01:22 +00:00
Bruno Cardoso Lopes
4d04362813 Fix comment order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 02:08:52 +00:00
Bruno Cardoso Lopes
8c05a850f4 Begin to support some vector operations for AVX 256-bit intructions. The long
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 02:06:36 +00:00
Johnny Chen
270159fcc2 The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 01:40:54 +00:00
Daniel Dunbar
09062b1672 MC/X86/AsmParser: Give an explicit error message when we reject an instruction
because it could have an ambiguous suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:55:42 +00:00
Daniel Dunbar
f1e29d4c21 MC/AsmParser: Push the burdon of emitting diagnostics about unmatched
instructions onto the target specific parser, which can do a better job.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:55:38 +00:00
Daniel Dunbar
4f98f83459 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',
target specific parsers can adapt the TargetAsmParser to this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:55:32 +00:00
Devang Patel
fd56f3c91a This is x86 only test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110887 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:17:38 +00:00
Daniel Dunbar
ee0f32d723 configure: Add detection of the linker version string.
- Review appreciated, as long as you understand that I understand that this is
   a horrible hack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:53:59 +00:00
Johnny Chen
7def14f40f Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:35:12 +00:00
Devang Patel
ebd53742c6 Even if a variable has constant value all the time, it is still a variable in gdb's eyes.
Tested by scope.exp in gdb testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:17:54 +00:00
Bob Wilson
eaf1c98a7c Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode.  This also fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:10:46 +00:00
Jakob Stoklund Olesen
d29583bd32 Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.
When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:08:22 +00:00
Owen Anderson
cf6abd2486 Fix a subtle use-after-free issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 22:36:04 +00:00
Nick Lewycky
7f9ef4bb51 Clean up ConstantRange a bit:
- remove ashr which never worked.
 - fix lshr and shl and add tests.
 - remove dead function "intersect1Wrapped".
 - add a new sub method to subtract ranges, with test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 22:04:36 +00:00
Bruno Cardoso Lopes
4fd393cc26 Add testcases for all AVX 256-bit intrinsics added in the last couple days
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 21:12:09 +00:00
Dan Gohman
bd4d66d56a Make LoopPass::getContainedPass return a LoopPass* instead of a Pass*
and remove casts from all its callers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 20:34:43 +00:00
Dan Gohman
fa5c2a67c3 Remove BasicBlockPass::runOnFunction, which was unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110847 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 20:28:16 +00:00
Bruno Cardoso Lopes
ec1355b17b Remove rsqrt/sqrt_nr intrinsics since there are no more builtins for them on clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 19:21:05 +00:00
Dan Gohman
1f9a1608a6 Delete FunctionPass::run, which is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 19:11:05 +00:00
Dan Gohman
73e8800229 Delete FunctionPass::runOnModule, which is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 19:05:53 +00:00
Dan Gohman
b68f274b6d Don't use unsigned char for alignments in TargetData. There aren't
that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 18:15:01 +00:00
Dan Gohman
d881627d33 Use ISD::ADD instead of ISD::SUB with a negated constant. This
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 18:14:00 +00:00
Bruno Cardoso Lopes
1d72aeebf9 Reapply r109881 using a more strict command line for llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110833 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:39:23 +00:00
Jim Grosbach
b5aa11f2d6 fix silly typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:32:46 +00:00
Jim Grosbach
7166e622d7 Add a target triple, as the runtime library invocation varies a bit by
platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110830 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:31:12 +00:00
Evan Cheng
e1f0859789 Fix test and re-enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 17:25:51 +00:00
Jakob Stoklund Olesen
dfa28b157d Fix a FIXME. The SlotIndex::Slot enum should be private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 16:50:17 +00:00
Dan Gohman
3cc5d13f58 Temporarily disable some failing tests, until they can be
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 16:36:07 +00:00
Jim Grosbach
fcba5e6b64 cortex m4 has floating point support, but only single precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 15:44:15 +00:00
Dan Gohman
f63fed141e Temporarily disable some failing tests, until they can be
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 15:09:00 +00:00
Bill Wendling
de2b151dbf Consider this code snippet:
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 08:43:16 +00:00
Evan Cheng
7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 07:17:46 +00:00
Evan Cheng
8d62e713ea ArchV7M implies HW division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 07:00:16 +00:00
Evan Cheng
cb5ce6e62b ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:57:53 +00:00
Evan Cheng
d6b4632256 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:51:54 +00:00