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6afb65c2b7
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Author SHA1 Message Date
Rafael Espindola
6afb65c2b7 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 01:48:30 +00:00
Rafael Espindola
6c1202c459 Handle relocations that don't point to symbols. 
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183284 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 01:33:53 +00:00
Vincent Lejeune
bbbdba891b R600: Add a pass that merge Vector Register 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d R600: Const/Neg/Abs can be folded to dot4 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:17:15 +00:00
Evan Cheng
00ed010d9e Cortex-R5 can issue Thumb2 integer division instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:52:09 +00:00
Arnold Schwaighofer
8a227084a5 Revert series of sched model patches until I figure out what is going on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
f500aa0b24 ARM sched model: Add VFP div instruction on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183271 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:08 +00:00
Arnold Schwaighofer
858f6f8899 ARM sched model: Add SIMD/VFP load/store instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183270 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:07 +00:00
Arnold Schwaighofer
e52041c16e ARM sched model: Add integer VFP/SIMD instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183269 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:05 +00:00
Arnold Schwaighofer
f3a2329d33 ARM sched model: Add integer load/store instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:04 +00:00
Arnold Schwaighofer
755d1295a5 ARM sched model: Add integer arithmetic instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183267 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:02 +00:00
Arnold Schwaighofer
eb9948e781 ARM sched model: Cortex A9 - More InstRW sched resources 
Add more InstRW mappings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183266 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:00 +00:00
Arnold Schwaighofer
002faf20a7 ARM sched model: Add branch thumb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:59 +00:00
Arnold Schwaighofer
16d915018b ARM sched model: Add branch thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183264 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:57 +00:00
Arnold Schwaighofer
36ea791280 ARM sched model: Add branch instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:56 +00:00
Arnold Schwaighofer
fdbca2faac ARM sched model: Add preload thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183262 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:54 +00:00
Arnold Schwaighofer
d3b8445d14 ARM sched model: Add preload instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183261 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:52 +00:00
Arnold Schwaighofer
23cb39a3d9 ARM sched model: Add more ALU and CMP thumb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183260 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:51 +00:00
Arnold Schwaighofer
1942e3254d ARM sched model: Add more ALU and CMP thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183259 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:49 +00:00
Arnold Schwaighofer
4c53731e5b ARM sched model: Add more ALU and CMP instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183258 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:47 +00:00
Arnold Schwaighofer
611c6e1359 ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:46 +00:00
Arnold Schwaighofer
ede7eeae32 ARMInstrInfo: Improve isSwiftFastImmShift 
An instruction with less than 3 inputs is trivially a fast immediate shift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183256 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:43 +00:00
Venkatraman Govindaraju
1e06bcbd63 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 18:33:25 +00:00
David Majnemer
35e7751af4 ARM: Fix crash in ARM backend inside of ARMConstantIslandPass 
The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.

This fixes PR16215.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183238 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 17:46:15 +00:00
Vincent Lejeune
98017a015b R600: Swizzle texture/export instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 15:04:53 +00:00
Vladimir Medic
164de54391 Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183215 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 08:28:53 +00:00
Aaron Ballman
f3d3952a8c Silencing an MSVC warning about mixing bool and unsigned int. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183176 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 01:03:03 +00:00
Tom Stellard
e5fcc0dee4 R600/SI: Add support for work item and work group intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:18 +00:00
Tom Stellard
e7397ee81a R600/SI: Add a calling convention for compute shaders 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:11 +00:00
Tom Stellard
e86f9d70ca R600/SI: Custom lower i64 sign_extend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:03 +00:00
Tom Stellard
17e8ad67f0 R600/SI: Adjust some instructions' out register class after ISel 
This is necessary to avoid generating VGPR to SGPR copies in some
cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183135 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:58 +00:00
Tom Stellard
b89a467559 R600/SI: Handle REG_SEQUENCE in fitsRegClass() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:54 +00:00
Tom Stellard
051a28e0e8 R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183133 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:50 +00:00
Tom Stellard
8a72c73032 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() 
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR.  This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else.  The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183132 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:46 +00:00
Tom Stellard
132183510f R600/SI: Add support for global loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183131 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:43 +00:00
Tom Stellard
4956bc61e1 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183130 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:37 +00:00
Vincent Lejeune
0c92287985 R600: 3 op instructions have no write bit but the result are store in PV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183111 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 15:56:12 +00:00
Vincent Lejeune
fdf7ab1c69 R600: CALL_FS consumes a stack size entry 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183108 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 15:44:42 +00:00
Vincent Lejeune
96fe0be43b R600: use capital letter for PV channel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 15:44:35 +00:00
Vincent Lejeune
0962e147a4 R600: Constraints input regs of interp_xy,_zw 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183106 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 15:44:16 +00:00
Ahmed Bougacha
b8ce45752b X86: sub_xmm registers are 128 bits wide. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183103 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 14:42:40 +00:00
Venkatraman Govindaraju
e7cbb792c9 Sparc: Add support for indirect branch and blockaddress in Sparc backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183094 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju
85cc972a06 Sparc: When storing 0, use %g0 directly in the store instruction instead of 
using two instructions (sethi and store).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju
65ca7aa57d Sparc: Combine add/or/sethi instruction with restore if possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183088 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju
dd48226b15 Sparc: Perform leaf procedure optimization by default 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183083 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju
a0b34d6c4a Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183079 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-01 20:42:48 +00:00
Tim Northover
3ba14fab1b Revert r183069: "TMP: LEA64_32r fixing" 
Very sorry, it was committed from the wrong branch by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-01 10:23:46 +00:00
Tim Northover
4d3ace4da0 TMP: LEA64_32r fixing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-01 10:21:54 +00:00
Tim Northover
85c622d6b6 X86: change MOV64ri64i32 into MOV32ri64 
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.

This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-01 09:55:14 +00:00
Venkatraman Govindaraju
72ad17c48c [Sparc] Generate correct code for leaf functions with stack objects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-01 04:51:18 +00:00