Commit Graph

19541 Commits

Author SHA1 Message Date
Rafael Espindola
6d6cbe3a3a Convert test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-12 16:35:53 +00:00
Ulrich Weigand
c1f4a4b264 [MC/DWARF] Support .debug_frame / .debug_line code alignment factors
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.

In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4.  However, current MC code hard-codes a code
alignment factor of 1.

This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.

This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc.  Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available.  However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it.  If it turns out to be needed again at a later time, it
could be re-added with an updated interface.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-12 14:46:54 +00:00
Ulrich Weigand
e48e8c7a60 [PowerPC] Use assembler source in MC tests
A couple of old test cases in test/MC/PowerPC were still using
LLVM IR.  Now that we have a working assembler, we can move
them to assembler tests instead:
  ppc64-initial-cfa.ll
  ppc64-relocs-01.ll
  ppc64-tls-relocs-01.ll




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-12 14:14:18 +00:00
Sean Silva
0d3b9ac634 [yaml2obj] Remove fragile test case.
This test case was a "sanity check"/"breathing" test case at first, but
is really fragile, which impairs changes to yaml2obj.

`test/Object/yaml2obj-elf-bits-endian.test` is much more robust and
serves as an adequate sanity check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183811 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-12 00:01:26 +00:00
Akira Hatanaka
45137f954f [mips] Add an IR transformation pass that optimizes calls to sqrt.
The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 22:21:44 +00:00
Rafael Espindola
d1b6ca23b4 Change how globalopt handles aliases in llvm.used.
Instead of a custom implementation of replaceAllUsesWith, we just call
replaceAllUsesWith and recreate llvm.used and llvm.compiler-used.

This change is particularity interesting because it makes llvm see
through what clang is doing with static used functions in extern "C"
contexts. With this change, running clang -O2 in

extern "C" {
  __attribute__((used)) static void foo() {}
}

produces

@llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to
i8*)], section "llvm.metadata"
define internal void @foo() #0 {
entry:
  ret void
}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 17:48:06 +00:00
NAKAMURA Takumi
6c921a55f4 Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 10:01:42 +00:00
Mihai Popa
55ab7315d0 It adds support for negative zero offsets for loads and stores.
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 09:48:35 +00:00
Mihai Popa
16ad92ad3c This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 09:39:51 +00:00
Amaury de la Vieuville
aa8003712e ARM: Enforce decoding rules for VLDn instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 08:14:14 +00:00
Amaury de la Vieuville
3862709058 ARM: Fix STREX/LDREX reecoding
The decoded MCInst wasn't reencoded as the same instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 08:03:20 +00:00
NAKAMURA Takumi
c139672407 Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
  - For now, The tests are marked as XFAIL for win32 hosts.

FIXME: Could we avoid XFAIL to specify triple in the RUN lines?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 06:52:58 +00:00
Sean Silva
457c8ebfd0 Fix dubious type name similar to member name.
Should bring bots back to life.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 00:13:52 +00:00
Sean Silva
5918b7a03d [yaml2obj] Initial ELF support.
Currently, only emitting the ELF header is supported (no sections or
segments).

The ELFYAML code organization is broadly similar to the COFFYAML code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183711 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 23:44:15 +00:00
Tim Northover
9bdd785014 ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.

rdar://14024354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 23:20:58 +00:00
Tim Northover
e5609f3732 X86: Stop LEA64_32r doing unspeakable things to its arguments.
Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.

This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 20:43:49 +00:00
Ulrich Weigand
278916500a [PowerPC] Support extended sc mnemonic
A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler.  This patch adds a corresponding alias.

Problem reported by Joerg Sonnenberger.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 17:19:43 +00:00
Ulrich Weigand
7c6f90d486 [PowerPC] Support branch mnemonics with implied CR0
The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified.  This patch
adds extra variants of the mnemonics to this effect.

Problem reported by Joerg Sonnenberger.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183686 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 17:19:15 +00:00
Amaury de la Vieuville
4e9a96d810 ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 14:17:08 +00:00
Justin Holewinski
7c32502a7f [NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183652 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 13:29:47 +00:00
JF Bastien
366d94e16c Add test for ARM FastISel load/store register classes
r183624 fixed an issue that was tested indirectly. Test it directly with this new test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 00:35:57 +00:00
Reed Kotler
b0ee97a366 Fix a regression I introduced when I expanded the complex pseudos in
the Mips16 port. A few of the psuedos could either take signed
or unsigned arguments and I did not distinguish the case and improperly
rejected some valid cases that the assembler had previously accepted
when they were pure pseudos that expanded as assembly instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 23:23:46 +00:00
Logan Chien
c8ecf53082 Refine the ARM EHABI test cases.
Since we have ARM unwind directive parser and assembler, we
can check the correctness in two stages:

1. From LLVM assembly (.ll) to ARM assembly (.s)
2. From ARM assembly (.s) to ELF object file (.o)

We already have several "*.s to *.o" test cases.  This CL adds
some "*.ll to *.s" test cases and removes the redundant "*.ll to *.o"
test cases.

New test cases to check "*.ll to *.s" code generator:

- ehabi.ll: Check the correctness of the generated unwind directives.
- section-name.ll: Check the section name of functions.

Removed test cases:

- ehabi-mc-cantunwind.ll
  (Covered by ehabi-cantunwind.ll, and eh-directive-cantunwind.s)
- ehabi-mc-compact-pr0.ll
  (Covered by ehabi.ll, eh-compact-pr0.s, eh-directive-save.s, and
   eh-directive-setfp.s)
- ehabi-mc-compact-pr1.ll
  (Covered by ehabi.ll, eh-compact-pr1.s, eh-directive-save.s, and
   eh-directive-setfp.s)
- ehabi-mc.ll
  (Covered by ehabi.ll, and eh-directive-integrated-test.s)
- ehabi-mc-section-group.ll
  (Covered by section-name.ll, and eh-directive-section-comdat.s)
- ehabi-mc-section.ll
  (Covered by section-name.ll, and eh-directive-section.s)
- ehabi-mc-sh_link.ll
  (Covered by eh-directive-text-section.s, and eh-directive-section.s)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183628 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 12:36:57 +00:00
Logan Chien
18cba562c8 Fix ARM unwind opcode assembler in several cases.
Changes to ARM unwind opcode assembler:

* Fix multiple .save or .vsave directives.  Besides, the
  order is preserved now.

* For the directives which will generate multiple opcodes,
  such as ".save {r0-r11}", the order of the unwind opcode
  is fixed now, i.e. the registers with less encoding value
  are popped first.

* Fix the $sp offset calculation.  Now, we can use the
  .setfp, .pad, .save, and .vsave directives at any order.

Changes to test cases:

* Add test cases to check the order of multiple opcodes
  for the .save directive.

* Fix the incorrect $sp offset in the test case.  The
  stack pointer offset specified in the test case was
  incorrect.  (Changed test cases: ehabi-mc-section.ll and
  ehabi-mc.ll)

* The opcode to restore $sp are slightly reordered.  The
  behavior are not changed, and the new output is same
  as the output of GNU as.  (Changed test cases:
  eh-directive-pad.s and eh-directive-setfp.s)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 12:22:30 +00:00
Elena Demikhovsky
40e071c1eb Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 07:37:10 +00:00
Tim Northover
d84b17e157 Make DeadArgumentElimination more conservative on variadic functions
Variadic functions are particularly fragile in the face of ABI changes, so this
limits how much the pass changes them

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 02:17:27 +00:00
Venkatraman Govindaraju
1799921672 [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183613 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 15:32:59 +00:00
Amaury de la Vieuville
9eefea009f ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:54:05 +00:00
Amaury de la Vieuville
ae50ddb2ae ARM: enforce SRS decoding constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:43:59 +00:00
Amaury de la Vieuville
46e136c952 ARM: fix CPS decoding when ambiguous with QADD
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS decoding as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:38:52 +00:00
Amaury de la Vieuville
c64835b0c5 ARM: fix VCVT decoding
UNPRED was reported instead of UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183608 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:29:11 +00:00
Shuxin Yang
9792b646c6 Fix a potential bug in r183584.
r183584 tries to derive some info from the code *AFTER* a call and apply
these derived info to the code *BEFORE* the call, which is not always safe
as the call in question may never return, and in this case, the derived
info is invalid.
  
  Thank Duncan for pointing out this potential bug.

rdar://14073661 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 04:56:05 +00:00
Quentin Colombet
c0cc28301a Reapply r183552. This time, use a standard type for the option to avoid template
instantiation issue with non-standard type.

Add a backend option to warn on a given stack size limit.
Option: -mllvm -warn-stack-size=<limit>
Output (if limit is exceeded):
warning: Stack size limit exceeded (<actual size>) in <functionName>.

The longer term plan is to hook that to a clang warning.
PR:4072
<rdar://problem/13987214>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183595 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 00:07:54 +00:00
Vincent Lejeune
b01bdf87ff R600: Anti dep better handled in tex clause
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 23:30:26 +00:00
Jakob Stoklund Olesen
7de1d327f1 Add missing zextloadi1 to i64 patterns. PR16721.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 22:55:05 +00:00
Shuxin Yang
1c2b03aae9 Fix an assertion in MemCpyOpt pass.
The MemCpyOpt pass is capable of optimizing:
      callee(&S); copy N bytes from S to D.
    into:
      callee(&D);
subject to some legality constraints. 

  Assertion is triggered when the compiler tries to evalute "sizeof(typeof(D))",
while D is an opaque-typed, 'sret' formal argument of function being compiled.
i.e. the signature of the func being compiled is something like this:
  T caller(...,%opaque* noalias nocapture sret %D, ...)

  The fix is that when come across such situation, instead of calling some
utility functions to get the size of D's type (which will crash), we simply
assume D has at least N bytes as implified by the copy-instruction.

rdar://14073661 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 22:45:21 +00:00
Hal Finkel
40be73bed7 Disallow i64 div/rem in PPC32 counter loops
On PPC32, [su]div,rem on i64 types are transformed into runtime library
function calls. As a result, they are not allowed in counter-based loops (the
counter-loops verification pass caught this error; this change fixes PR16169).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183581 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 22:16:19 +00:00
Quentin Colombet
95f24fbe4c Revert commits related to stack warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183579 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 22:14:50 +00:00
Quentin Colombet
2e10e8e378 Explicit triple in warn stack size test cases to not depend on OS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183574 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 21:09:42 +00:00
Tom Stellard
df74b86e1e R600: Fix calculation of stack offset in AMDGPUFrameLowering
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:52:05 +00:00
Tom Stellard
ce961477be R600: Fix the fetch limits for R600 generation GPUs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183560 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:28:55 +00:00
Quentin Colombet
9a6b9bffa5 Add a backend option to warn on a given stack size limit.
Option: -mllvm -warn-stack-size=<limit>
Output (if limit is exceeded):
warning: Stack size limit exceeded (<actual size>) in <functionName>.

The longer term plan is to hook that to a clang warning.
PR:4072
<rdar://problem/13987214>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183552 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:18:12 +00:00
JF Bastien
8fc760cbe8 ARM FastISel integer sext/zext improvements
My recent ARM FastISel patch exposed this bug:
  http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.

The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.

fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).

2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.

fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.

Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.

I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:10:37 +00:00
Quentin Colombet
fcca6c690c Teach AsmPrinter how to print odd constants.
Fix an assertion when the compiler encounters big constants whose bit width is
not a multiple of 64-bits.
Although clang would never generate something like this, the backend should be
able to handle any legal IR.

<rdar://problem/13363576>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 18:36:03 +00:00
Roman Divacky
6ca5fd3f30 Fix a typo in asm string of BP* family of instructions. With this fix
I am able to compile/assemble/link/run /bin/echo from FreeBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 17:46:57 +00:00
Rafael Espindola
62ed8d3e35 Support OpenBSD's native frame protection conventions.
OpenBSD's stack smashing protection differs slightly from other
platforms:

  1. The smash handler function is "__stack_smash_handler(const char
     *funcname)" instead of "__stack_chk_fail(void)".

  2. There's a hidden "long __guard_local" object that gets linked
     into each executable and DSO.

Patch by Matthew Dempsky.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183533 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 16:35:57 +00:00
Michael Gottesman
9eb856bc29 [objc-arc] Ensure that the cfg path count does not overflow when we multiply TopDownPathCount/BottomUpPathCount.
rdar://12480535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 06:16:49 +00:00
Venkatraman Govindaraju
01021a8b93 [Sparc]: Use cmp instruction instead of subcc to compare integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 00:03:36 +00:00
Kevin Enderby
285bd8e6f9 Move the test for the data in code into the ARM directory as it is an ARM
binary that is used for the test.  Caught by Jim Grosbach!

rdar://11791371


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 20:28:28 +00:00
Rafael Espindola
ab9ba5321d Add a testcase from pr16244.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 19:15:23 +00:00