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52 Commits

Author SHA1 Message Date
Jim Grosbach
0ede14f5c0 remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-27 23:06:27 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-03 18:15:48 +00:00
Dan Gohman
f5aeb1a8e4 Rename ConstantSDNode::getValue to getZExtValue, for consistency 
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-12 16:56:44 +00:00
Evan Cheng
130966411f More refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 06:41:12 +00:00
Chris Lattner
ddf89566a9 This commit changes: 
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-17 19:59:44 +00:00
Chris Lattner
9b37aaf04c get def use info more correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-10 05:12:37 +00:00
Evan Cheng
325474e065 Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45727 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-07 23:56:57 +00:00
Chris Lattner
834f1ce031 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 23:38:27 +00:00
Chris Lattner
2e48a70b35 rename isStore -> mayStore to more accurately reflect what it captures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 08:36:04 +00:00
Chris Lattner
13c6310866 remove explicit isStore flags that are now inferrable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45653 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-06 05:55:01 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Bill Wendling
0f8d9c04d9 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-11-13 00:44:25 +00:00
Evan Cheng
071a279e94 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-11 19:55:27 +00:00
Evan Cheng
0ff94f7fcc Initial JIT support for ARM by Raul Fernandes Herbster. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-07 01:37:15 +00:00
Evan Cheng
ffbaccae02 No more noResults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-21 00:34:19 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Evan Cheng
13ab020ea0 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-10 18:08:01 +00:00
Evan Cheng
9ad6f03166 No need for ccop anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-06 23:34:09 +00:00
Evan Cheng
c85e832eb7 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-05 07:13:32 +00:00
Dan Gohman
d45eddd214 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-26 00:48:07 +00:00
Dan Gohman
82a87a0172 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-19 01:26:51 +00:00
Evan Cheng
f81dea45b5 tBcc is not a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37516 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-08 09:13:23 +00:00
Evan Cheng
2c614c5c69 Mark these instructions clobbersPred. They modify the condition code register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-06 10:17:05 +00:00
Evan Cheng
3f8602cf20 ARM::tB is also predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37125 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:53:43 +00:00
Evan Cheng
44bec52b1b Add PredicateOperand to all ARM instructions that have the condition field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-15 01:29:07 +00:00
Evan Cheng
42d712b306 Switch BCC, MOVCCr, etc. to PredicateOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-08 21:08:43 +00:00
Evan Cheng
1b20168433 Doh. PC displacement is between the constantpool and the add instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36630 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-01 20:27:19 +00:00
Lauro Ramos Venancio
64f4fa5e0e ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36506 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 13:54:47 +00:00
Evan Cheng
eec041a037 Back out previous check-in. Incorrect. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36503 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 07:50:02 +00:00
Evan Cheng
33fdc983fd tLEApcrel is a AddrModeTs, i.e. pc relative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36502 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-27 07:37:22 +00:00
Lauro Ramos Venancio
9996663fc6 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-02 01:30:03 +00:00
Evan Cheng
5e3c203cfd Can't re-materialize mov r, imm in thumb since mov would clobber the condition code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35479 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-29 21:38:31 +00:00
Lauro Ramos Venancio
b8a93a45f8 bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-27 16:19:21 +00:00
Lauro Ramos Venancio
64c88d741e bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35218 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-20 17:57:23 +00:00
Evan Cheng
9f6636ff0c Fix naming inconsistencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:48:02 +00:00
Evan Cheng
fa775d09c6 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:20:03 +00:00
Evan Cheng
a251570417 Constant generation instructions are re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-19 07:09:02 +00:00
Evan Cheng
8e59ea998f Spill / restore should avoid modifying the condition register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33971 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-07 00:06:56 +00:00
Evan Cheng
e0c2b6b9a8 .set pc relative displacement bug: label should be moved down one instruction 
to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33744 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 03:04:49 +00:00
Evan Cheng
9d945f78e5 Special epilogue for vararg functions. We cannot do a pop to pc because 
there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33739 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-01 01:49:46 +00:00
Evan Cheng
3471b60e95 Thumb asm syntax does not want 's' suffix for flag setting opcodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33717 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-31 20:12:31 +00:00
Evan Cheng
c60e76d139 - Fix codegen for pc relative constant (e.g. JT) in thumb mode: 
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33664 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-30 20:37:08 +00:00
Evan Cheng
cea117d2de Change the operand orders to t_addrmode_s* to make it easier to morph 
instructions that use these address modes to instructions that use
t_addrmode_sp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33651 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-30 02:35:32 +00:00
Evan Cheng
225dfe973b Use BL to implement Thumb far jumps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33649 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-30 01:13:37 +00:00
Evan Cheng
d85ac4d079 Thumb jumptable support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33568 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-27 02:29:45 +00:00
Evan Cheng
53d7dbafc3 Thumb add / sub with carry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33562 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-27 00:07:15 +00:00
Evan Cheng
3fdadfc9ab Represent tADDspi and tSUBspi as two-address instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33551 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-26 21:33:19 +00:00
Evan Cheng
b60c02e005 extload -> zextload 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33542 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-26 19:13:16 +00:00
Evan Cheng
012f2d97b7 Use PC relative ldr to load from a constantpool in Thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33484 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-24 08:53:17 +00:00