Commit Graph

103664 Commits

Author SHA1 Message Date
Rafael Espindola
73306ce39f Revert "ARMEB: Fix byte order of EH frame unwinding instructions"
This reverts commit r208689.

The test was crashing on OS X and windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208704 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 15:19:56 +00:00
Aaron Ballman
b37b01d95c Teach the table generator to not generate switch statements containing only a default label with no cases. This solves some warnings with MSVC.
No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208694 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 12:52:35 +00:00
Christian Pirker
3beea23c1b ARM: Additional test files for thumb fixups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208691 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 11:50:39 +00:00
Daniel Sanders
0e0f907356 [mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-3 that was available in MIPS32R2.

To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3696

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 11:45:36 +00:00
Christian Pirker
34b9ca5e14 ARMEB: Fix byte order of EH frame unwinding instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208689 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 11:41:49 +00:00
Daniel Sanders
fc2427bcf8 [mips] Free up two values in SubtargetFeatureFlag by folding the redundant IsGP32/IsGP64 into IsGP32bit/IsGP64bit
Summary:
We are currently very close to the 32-bit limit of the current assembler
implementation. This is because there is no way to represent an instruction
that is available in, for example, Mips3 or Mips32. We have to define a
feature bit that represents this.

This patch cleans up a pair of redundant feature bits and slightly postpones the
point we will reach the limit.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3703

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208685 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 11:17:46 +00:00
Artyom Skrobov
56db241e8b Fix build failure with MSVC, following r208680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208684 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 11:16:22 +00:00
Artyom Skrobov
8d9fa8f2dd include/llvm/Support/Unicode.h didn't have re-include guards
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 10:11:29 +00:00
Artyom Skrobov
04b617977e [un]wrap extracted from lib/Target/Target[MachineC].cpp, lib/ExecutionEngine/ExecutionEngineBindings.cpp into include/llvm/IR/DataLayout.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208680 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 09:45:26 +00:00
Tim Northover
e9592d0838 TableGen: strengthen assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208679 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 09:37:41 +00:00
Jay Foad
ae0a8337f2 Fix gcc -Wparentheses warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208675 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 08:26:53 +00:00
Kevin Qin
2a74dfe388 [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode.
A vague diagnostic replaced the misleading one.
This can fix bug 19502.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 07:35:12 +00:00
Serge Pavlov
51a167d6c4 Fix type of shuffle resulted from shuffle merge.
This fix resolves PR19730.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208666 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 06:07:21 +00:00
Rafael Espindola
e2b37447b7 Assert that we don't RAUW a Constant with a ConstantExpr that contains it.
We already had an assert for foo->RAUW(foo), but not for something like
foo->RAUW(GEP(foo)) and would go in an infinite loop trying to apply
the replacement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208663 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 01:23:21 +00:00
Weiming Zhao
0449d522a6 Folding into CSEL when there is ZEXT between SETCC and ADD
Normally, patterns like (add x, (setcc cc ...)) will be folded into
(csel x, x+1, not cc). However, if there is a ZEXT after SETCC, they
won't be folded. This patch recognizes the ZEXT and allows the
generation of CSINC.

This patch fixes bug 19680.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 00:40:58 +00:00
Rafael Espindola
5204fedd35 Convert test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 00:31:31 +00:00
Rafael Espindola
151e34116a Convert test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13 00:07:46 +00:00
David Blaikie
47290de5db Revert "DebugInfo: Include lexical scopes in inlined subroutines."
This reverts commit r208506.

Some inlined subroutine scopes appear to be missing with this change.
Reverting while I investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208642 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 23:53:03 +00:00
Pete Cooper
5a5a0640d8 Use a logical not when inverting SetCC. This unfortunately doesn't fire on any targets so I couldn't find a test case to trigger it.
The problem occurs when a non-i1 setcc is inverted.  For example 'i8 = setcc' will get 'xor 0xff' to invert this.   This is clearly wrong when the boolean contents are ZeroOrOne.

This patch introduces getLogicalNOT and updates SetCC legalisation to use it.

Reviewed by Hal Finkel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208641 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 23:26:58 +00:00
Adam Nemet
73282018a1 [DAGCombiner] Split up an indexed load if only the base pointer value is live
Right now the load may not get DCE'd because of the side-effect of updating
the base pointer.

This can happen if we lower a read-modify-write of an illegal larger type
(e.g. i48) such that the modification only affects one of the subparts (the
lower i32 part but not the higher i16 part).  See the testcase.

In order to spot the dead load we need to revisit it when SimplifyDemandedBits
decided that the value of the load is masked off.  This is the
CommitTargetLoweringOpt piece.

I checked compile time with ARM64 by sending SPEC bitcode files through llc.
No measurable change.

Fixes <rdar://problem/16031651>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208640 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 23:00:03 +00:00
Louis Gerbarg
1633f752f8 Fix ARM bswap16.ll test on Windows
Windows on ARM only supports thumb mode execution, so we have to
explicitly pick some non-Windows OS to test ARM mode codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208638 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 22:13:07 +00:00
Reid Kleckner
17335ce80f Try to fix an SDAG dependence issue with sret
r208453 added support for having sret on the second parameter.  In that
change, the code for copying sret into a virtual register was hoisted
into the loop that lowers formal parameters.  This caused a "Wrong
topological sorting" assertion failure during scheduling when a
parameter is passed in memory.  This change undoes that by creating a
second loop that deals with sret.

I'm worried that this fix is incomplete.  I don't fully understand the
dependence issues.  However, with this change we produce the same DAGs
we used to produce, so if they are broken, they are just as broken as
they have always been.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208637 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 22:01:27 +00:00
David Blaikie
03e19bb235 DebugInfo: Attach DW_AT_inline to inlined subprograms at DIE-construction time rather than as a post-processing step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 21:50:44 +00:00
Lang Hames
b572bc1ccf [RuntimeDyld] Add support for MachO __jump_table and __pointers sections, and
SECTDIFF relocations on 32-bit x86.

This fixes several of the MCJIT regression test failures that show up on 32-bit
builds.

<rdar://problem/16886294>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 21:39:59 +00:00
David Blaikie
6124834147 DebugInfo: Make gmlt debug info more gmlt-like by removing variables.
For some impending improvements to debug info, LLVM will start assuming
that when the CU specifies llvm::DIBuilder::LineTablesOnly, the IR for
functions described by that CU will not include variables, types, etc.

(might be worth having some test coverage for GMLT + non-GMLT CUs,
especially with non-GMLT functions inlined into GMLT CU functions)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 21:33:03 +00:00
Kevin Enderby
e1541915f0 Suggested improvement by Rafael Espindola to use isa<> in a few places
instead of dyn_cast<>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 20:45:00 +00:00
Matt Arsenault
8655b1266f Use cast<> for unchecked use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208627 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 20:42:57 +00:00
Sebastian Pop
d2b27bba87 use nullptr instead of NULL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 20:11:01 +00:00
Adam Nemet
45fc47013f [Test] Trim unnecessary .c and .cpp from config.suffix in lit.local.cfg
Tested by comparing make check VERBOSE=1 before and after to make sure
no tests are missed.  (VERBOSE=1 prints the list of tests.)

Only one test :( remains where .cpp is required:

tools/llvm-cov/range_based_for.cpp:// RUN: llvm-cov range_based_for.cpp | FileCheck %s --check-prefix=STDOUT

The topic was discussed in this thread:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:57:31 +00:00
Louis Gerbarg
9cec62a27f Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb
The current patterns for REV16 misses mostn __builtin_bswap16() due to
legalization promoting the operands to from load/stores toi32s and then
truncing/extending them. This patch adds new patterns that catch the resultant
DAGs and codegens them to rev16 instructions. Tests included.

rdar://15353652

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208620 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:53:52 +00:00
Matt Arsenault
b36e348af3 Use cast<> for unchecked use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:26:38 +00:00
Matt Arsenault
76aa42c199 Use range for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208617 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:23:21 +00:00
Sebastian Pop
2f5f1c2ccb do not assert when delinearization fails
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:01:53 +00:00
Sebastian Pop
d9673ebd34 use isZero()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:01:49 +00:00
David Blaikie
9f84cecfdc DwarfDebug: Avoid an extra map lookup while constructing abstract scope DIEs and reduce nesting/conditionals.
One test case had to be updated as it still had the extra indirection
for the variable list - removing the extra indirection got it back to
passing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208608 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 18:23:35 +00:00
Tim Northover
d6cd0381f6 TableGen: use PrintMethods to print more aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 18:04:06 +00:00
Tim Northover
2161fd6114 AArch64/ARM64: use InstAliases for NEON logical (imm) instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208606 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 18:03:42 +00:00
Tim Northover
c56a5421b8 AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.
This is a slightly different approach to AArch64 (the base instruction
definitions aren't quite right for that to work), but achieves the
same thing and reduces C++ hackery in AsmParser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 18:03:36 +00:00
Matt Arsenault
5049ca67c2 R600: Add mul24 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 17:49:57 +00:00
Matt Arsenault
621299806c Make SimplifyDemandedBits understand BUILD_PAIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208598 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 17:14:48 +00:00
Matheus Almeida
db5b7e016a [mips] Move disassembler test (test_2r_msa64) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208594 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:59:34 +00:00
Matheus Almeida
4d28469a8d [mips] Move disassembler test (Mips MSA test_vec) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208592 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:31:45 +00:00
Matheus Almeida
d8527e2578 [mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208590 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:26:53 +00:00
Matheus Almeida
e9cd60685b [mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208589 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:23:45 +00:00
Matheus Almeida
e18828fb2b [mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:20:46 +00:00
Matheus Almeida
f666827156 [mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:16:59 +00:00
Matheus Almeida
86992065e6 [mips] Move disassembler test (Mips MSA test_bit) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208586 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:10:00 +00:00
Matheus Almeida
5e3662ae95 [mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf) into
correct folder.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:03:20 +00:00
Daniel Sanders
e44de6afea Revert: r208582 - [mips][mips64r6] Add sel.s and sel.d
Accidentally committed an unreviewed patch. Reverted it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:43:41 +00:00
Daniel Sanders
87010f33a8 [mips][mips64r6] Add sel.s and sel.d
Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: jkolek, vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D3670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 15:39:10 +00:00