Commit Graph

54441 Commits

Author SHA1 Message Date
Akira Hatanaka
739572f069 Remove MipsEmitGPRestore.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 03:24:03 +00:00
Akira Hatanaka
8f16ab5bab Delete all functions that are no longer needed in MipsFunctionInfo, including
the ones that get or set the frame index for the $gp save slot. 

Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns
GP. This function should always return a virtual register.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 03:22:13 +00:00
Akira Hatanaka
93f0a823bf Stop reserving register $gp. Do not call isGPFI to check whether a frame object
is the $gp save slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 03:21:18 +00:00
Akira Hatanaka
acf411bd4c Do not add the pass which restores $gp after every function call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156693 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 03:19:51 +00:00
Akira Hatanaka
92d4aec573 Make the following changes in MipsISelLowering.cpp:
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 03:19:04 +00:00
Akira Hatanaka
30cec40241 Make the following changes in MipsFrameLowering.cpp:
- Stop emitting instructions needed to initialize the global pointer register.
- Stop emitting .cprestore directive.
- Do not take into account the $gp save slot when computing stack size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156691 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 03:18:00 +00:00
Akira Hatanaka
4147e4d054 Make the following changes in MipsAsmPrinter.cpp:
- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 00:48:43 +00:00
Chad Rosier
774394c68a Hoist simpler checks above llvm::PointerMayBeCaptured. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 00:43:40 +00:00
Jakob Stoklund Olesen
2b3fa322b8 Don't look for empty live ranges in the unions.
Empty live ranges represent undef and still get allocated, but they
won't appear in LiveIntervalUnions.

Patch by Patrik Hägglund!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 00:33:28 +00:00
Akira Hatanaka
27ba61df9f Insert instructions to the entry basic block which initializes the global
pointer register. 


This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12 00:17:17 +00:00
Akira Hatanaka
3011a33a63 Do not replace operands of pseudo instructions with register $zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156663 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 23:22:18 +00:00
Chad Rosier
aefd36bdda Revert 156658.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156662 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 23:21:01 +00:00
Chad Rosier
550a08a876 [fast-isel] Fast-isel doesn't use the expect intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 23:10:58 +00:00
Michael J. Spencer
b0940b46ed [Support/StringRef] Add find_last_not_of and {r,l,}trim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 22:08:50 +00:00
Chad Rosier
226ddf5278 [fast-isel] Add support for selecting @llvm.trap().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 21:33:49 +00:00
Brendon Cahoon
927ede5a87 Updated instruction table due to addded intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 21:10:16 +00:00
Sirish Pande
12a52525e8 Remove warnings from HexagonVLIWPacketizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156636 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 20:00:34 +00:00
Brendon Cahoon
6d532d8860 Hexagon constant extender support.
Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:56:59 +00:00
Chad Rosier
e1093e5503 Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156633 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:43:29 +00:00
Chad Rosier
2b3b335f2d [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:40:25 +00:00
Sirish Pande
81e900d14c Hexagon V5 intrinsics support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:39:13 +00:00
Chad Rosier
2a2e9d54e9 [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 18:51:55 +00:00
Nuno Lopes
12c807873a objectsize: add a few more tests and fix a bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 18:25:29 +00:00
Chad Rosier
2f6ae41f14 [fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 17:41:06 +00:00
Chad Rosier
f4bd21c256 The return type is an unsigned, not a bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 16:41:38 +00:00
Manman Ren
4949e98ccc Add space before an open parenthesis in control flow statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 15:36:46 +00:00
Preston Gurd
3c579c8343 Added X86 Atom latencies to X86InstrMMX.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 14:27:12 +00:00
Hans Wennborg
228756c744 Implement initial-exec TLS model for 32-bit PIC x86
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 10:11:01 +00:00
Silviu Baranga
169e9ba2b2 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 09:28:27 +00:00
Silviu Baranga
ca3cd419a5 Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 09:10:54 +00:00
Akira Hatanaka
2b7ab5eb49 Fix a misleading comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 01:45:15 +00:00
Jim Grosbach
2684d9e3c7 Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 01:41:30 +00:00
Eli Friedman
5b6dfee28e Fix a minor logic mistake transforming compares in instcombine. PR12514.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 01:32:59 +00:00
Manman Ren
247c5ab07c ARM: peephole optimization to remove cmp instruction
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 01:30:47 +00:00
Dan Gohman
d4347e1af9 Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
but it generates int3 on x86 instead of ud2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 00:19:32 +00:00
Eric Christopher
61aef8bdf7 Allow unique_file to take a mode for file permissions, but default
to user only read/write.

Part of rdar://11325849

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 00:07:44 +00:00
Chad Rosier
620ee81fa0 Fix intendation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:38:07 +00:00
Nuno Lopes
9d236f909c objectsize: add support for GEPs with non-constant indexes
add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156585 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 23:17:35 +00:00
Preston Gurd
deaa3f3e52 Added X86 Atom latencies for instructions in X86InstrInfo.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:58:35 +00:00
Eric Christopher
05b7a50210 Add support for the 'X' inline asm operand modifier.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:48:22 +00:00
Andrew Trick
89c324bf11 misched: Print machineinstrs with -debug-only=misched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:21 +00:00
Andrew Trick
28ebc89c41 misched: tracing register pressure heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:19 +00:00
Andrew Trick
7196a8ff21 misched: Add register pressure backoff to ConvergingScheduler.
Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.

WIP: This is mostly functional but untested and not likely to do much good yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:16 +00:00
Andrew Trick
16716c7302 misched: Release only unscheduled nodes into ReadyQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:14 +00:00
Andrew Trick
d38f87eeec misched: Added ReadyQ container wrapper for Top and Bottom Queues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:12 +00:00
Andrew Trick
7f8ab785af misched: Introducing Top and Bottom register pressure trackers during scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 21:06:10 +00:00
Sirish Pande
0cfb5cfe97 Hexagon V5 Support - V5 td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 20:24:28 +00:00
Sirish Pande
7517bbc91a Hexagon V5 FP Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 20:20:25 +00:00
Andrew Trick
55ba5dff3c RegPressure: API for speculatively checking instruction pressure.
Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the
tracker by speculatively handling an instruction out of order. But it
is convenient for now. In the future, we will cache each instruction's
pressure contribution to make this efficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 19:11:52 +00:00
Andrew Trick
d253035339 RegPressure: fix array index iteration style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10 19:11:49 +00:00