Evan Cheng
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80a119842d
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Fix VFP conversion instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59104 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-12 06:41:41 +00:00 |
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Evan Cheng
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d06d48d2b5
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Fix encoding of single-precision VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59102 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-12 02:19:38 +00:00 |
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Evan Cheng
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0a0ab1387a
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Fix FMDRR encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59088 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-11 22:46:12 +00:00 |
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Evan Cheng
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cd8e66a1ef
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Encode VFP load / store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59084 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-11 21:48:44 +00:00 |
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Evan Cheng
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78be83d7c2
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Encode VFP conversion instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59074 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-11 19:40:26 +00:00 |
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Evan Cheng
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96581d3633
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Encode VFP arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59016 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-11 02:11:05 +00:00 |
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Evan Cheng
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d87293ce78
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Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-11-06 08:47:38 +00:00 |
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Jim Grosbach
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e5d20f947a
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udpate header comment: s/VP/VFP/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56126 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-09-11 21:41:29 +00:00 |
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Evan Cheng
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da47e6e0d0
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Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-03-15 00:03:38 +00:00 |
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Chris Lattner
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48be23cd65
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rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-01-15 22:02:54 +00:00 |
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Chris Lattner
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9b37aaf04c
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get def use info more correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-01-10 05:12:37 +00:00 |
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Evan Cheng
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325474e065
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Only mark instructions that load a single value without extension as isSimpleLoad = 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45727 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-01-07 23:56:57 +00:00 |
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Chris Lattner
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834f1ce031
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rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-01-06 23:38:27 +00:00 |
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Chris Lattner
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2e48a70b35
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rename isStore -> mayStore to more accurately reflect what it captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-01-06 08:36:04 +00:00 |
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Chris Lattner
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13c6310866
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remove explicit isStore flags that are now inferrable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45653 91177308-0d34-0410-b5e6-96231b3b80d8
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2008-01-06 05:55:01 +00:00 |
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Chris Lattner
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4ee451de36
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Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-12-29 20:36:04 +00:00 |
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Evan Cheng
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6e141fd048
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Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-12-12 23:12:09 +00:00 |
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Evan Cheng
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071a279e94
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Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-09-11 19:55:27 +00:00 |
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Evan Cheng
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0ff94f7fcc
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Initial JIT support for ARM by Raul Fernandes Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-08-07 01:37:15 +00:00 |
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Evan Cheng
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64d80e3387
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-07-19 01:14:50 +00:00 |
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Evan Cheng
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13ab020ea0
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Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-07-10 18:08:01 +00:00 |
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Evan Cheng
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9ad6f03166
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No need for ccop anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-07-06 23:34:09 +00:00 |
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Evan Cheng
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c85e832eb7
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Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-07-05 07:13:32 +00:00 |
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Evan Cheng
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2c614c5c69
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Mark these instructions clobbersPred. They modify the condition code register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-06-06 10:17:05 +00:00 |
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Evan Cheng
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c6f2f6fbb9
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For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-05-29 23:34:19 +00:00 |
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Evan Cheng
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44bec52b1b
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Add PredicateOperand to all ARM instructions that have the condition field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-05-15 01:29:07 +00:00 |
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Evan Cheng
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42d712b306
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Switch BCC, MOVCCr, etc. to PredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-05-08 21:08:43 +00:00 |
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Evan Cheng
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c4e600362e
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This is no longer needed after enabling the DAG combiner xform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36909 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-05-07 21:29:41 +00:00 |
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Dale Johannesen
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4ac075c859
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Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-05-03 20:54:42 +00:00 |
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Chris Lattner
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72939126d4
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match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-05-03 00:32:00 +00:00 |
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Evan Cheng
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a8e2989ece
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ARM backend contribution from Apple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
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2007-01-19 07:51:42 +00:00 |
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