Commit Graph

435 Commits

Author SHA1 Message Date
Craig Topper
bd01df2487 Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-19 06:10:58 +00:00
Kevin Qin
74287ec34c [AArch64] Fix a pattern match failure caused by creating improper CONCAT_VECTOR.
ReconstructShuffle() may wrongly creat a CONCAT_VECTOR trying to
concat 2 of v2i32 into v4i16. This commit is to fix this issue and
try to generate UZP1 instead of lots of MOV and INS.
Patch is initalized by Kevin Qin, and refactored by Tim Northover.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211144 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 05:54:42 +00:00
Craig Topper
10d664fee7 Replace some assert(0)'s with llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211141 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 05:05:13 +00:00
Tim Northover
c22960dba6 AArch64: estimate inline asm length during branch relaxation
To make sure branches are in range, we need to do a better job of estimating
the length of an inline assembly block than "it's probably 1 instruction, who'd
write asm with more than that?".

Fortunately there's already a (highly suspect, see how many ways you can think
of to break it!) callback for this purpose, which is used by the other targets.

rdar://problem/17277590

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211095 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-17 11:31:42 +00:00
Jim Grosbach
44d2cdcbf3 AArch64: Add backend intrinsic for rbit.
Define an intrinsic for the frontend to use and pattern match it to
the RBIT instruction.

rdar://9283021

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211058 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-16 21:55:35 +00:00
Tilmann Scheller
d492c19894 [AArch64] Remove dead code.
Both function declarations lack a callee and an implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211029 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-16 15:15:41 +00:00
James Molloy
b3820b4289 [AArch64] Fix a fencepost error in lowering for llvm.aarch64.neon.uqshl.
Patch by Jiangning Liu!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211014 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-16 10:39:21 +00:00
Tim Northover
8bfc50e4a9 AArch64: improve handling & modelling of FP_TO_XINT nodes.
There's probably no acatual change in behaviour here, just updating
the LowerFP_TO_INT function to be more similar to the reverse
implementation and updating costs to current CodeGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210985 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 09:27:15 +00:00
Tim Northover
94fe5c1fe2 AArch64: improve vector [su]itofp handling.
This somehow got missed in the AArch64 merge, so should fix a
performance regression since 3.4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210984 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-15 09:27:06 +00:00
Chad Rosier
2e4cd27799 [AArch64] Basic Sched Model for Cortex-A57.
Patch by Dave Estes<cestes@codeaurora.org>
Differential Revision: http://reviews.llvm.org/D4008

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210705 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 21:06:56 +00:00
Eric Christopher
e290e4abc3 Move to a private function to initialize the subtarget dependencies
so that we can use initializer lists for the AArch64 Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-11 00:46:34 +00:00
Eric Christopher
fe80185273 Move AArch64TargetLowering to AArch64Subtarget.
This currently necessitates a TargetMachine for the TargetLowering
constructor and TLOF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 23:26:45 +00:00
Eric Christopher
159e408563 Move AArch64InstrInfo to AArch64Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210599 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 22:57:25 +00:00
Eric Christopher
468a0ce16f Remove a method that was just replacing direct access to a member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210598 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 22:57:21 +00:00
Eric Christopher
30ad4cb09b Move AArch64SelectionDAGInfo down to the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210557 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:21:53 +00:00
Eric Christopher
75b55475bc Remove the cached little endian variable. We can get it easily off
of the DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210555 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:11:20 +00:00
Eric Christopher
b8dca33a05 Have AArch64SelectionDAGInfo take a DataLayout parameter rather
than a TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210554 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:06:28 +00:00
Eric Christopher
e3a06bcd8a Remove caching of the subtarget for AArch64SelectionDAGInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210553 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:06:25 +00:00
Eric Christopher
fc0f6e8cc5 Move DataLayout onto the AArch64 subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210552 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 18:06:23 +00:00
Eric Christopher
c4f9370391 Move AArch64FrameLowering into the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210549 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 17:44:12 +00:00
Eric Christopher
8128a7965f Remove the uses of AArch64TargetMachine and AArch64Subtarget from
AArch64FrameLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210548 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 17:33:39 +00:00
Chad Rosier
0db9526c1a [AArch64] Emit .ident compiler version attribute.
Patch by Ana Pazos<apazos@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210535 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 14:32:08 +00:00
Artyom Skrobov
45a31492d5 Condition codes AL and NV are invalid in the aliases that use
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).

Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.

The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 13:11:35 +00:00
Tim Northover
e1db6ac10b AArch64: disallow x30 & x29 as the destination for indirect tail calls
As Ana Pazos pointed out, these have to be restored to their incoming values
before a function returns; i.e. before the tail call. So they can't be used
correctly as the destination register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210525 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 10:50:24 +00:00
Tim Northover
46b3076cd0 AArch64: teach FastISel how to handle offset FrameIndices
Previously we were abandonning the attempt, leading to some combination of
extra work (when selection of a load/store fails completely) and inferior code
(when this leads to a real memcpy call instead of inlining).

rdar://problem/17187463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210520 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 09:52:44 +00:00
Tim Northover
292c7c6a48 AArch64: make FastISel memcpy emission more robust.
We were hitting an assert if FastISel couldn't create the load or store we
requested. Currently this happens for large frame-local addresses, though
CodeGen could be improved there.

rdar://problem/17187463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 09:52:40 +00:00
Artyom Skrobov
a8d18fe946 [AArch64] Missing aliases for CMP/CMN [W]SP with no shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 11:10:14 +00:00
Chad Rosier
451cc566c1 [AArch64] Fix the ordering of the accumulate operand in SchedRW list.
Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D4037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210446 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 01:54:00 +00:00
Chad Rosier
0607e82c0a [AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift
plus add.  The shift can be folded into the add.  This only effects codegen
when the constant is 3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210445 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 01:25:51 +00:00
Craig Topper
b177041dfa [C++11] Use 'nullptr'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210442 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 22:29:17 +00:00
David Blaikie
c50f986b4d AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperand
I saw at least a memory leak or two from inspection (on probably
untested error paths) and r206991, which was the original inspiration
for this change.

I ran this idea by Jim Grosbach a few weeks ago & he was OK with it.
Since it's a basically mechanical patch that seemed sufficient - usual
post-commit review, revert, etc, as needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 16:18:35 +00:00
Alp Toker
aa59bc24a5 Remove outdated CMake MSVC workaround
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210421 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 07:37:17 +00:00
Eric Christopher
5448320a20 Have TargetSelectionDAGInfo take a DataLayout initializer rather than
a TargetMachine since the only thing it wants is DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210366 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-06 19:04:48 +00:00
Tilmann Scheller
45a8d99f59 [AArch64] clang-format the load/store optimizer.
No change in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210182 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-04 12:40:35 +00:00
Tilmann Scheller
b2caf9766e [AArch64] Fix some LLVM Coding Standards violations in the load/store optimizer.
Variable names should start with an upper case letter.

No change in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210181 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-04 12:36:28 +00:00
Tilmann Scheller
1514ecc83a [AArch64] Fix typo in load/store optimizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210114 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-03 16:33:13 +00:00
Tim Northover
1410a2c906 AArch64: mark small types (i1, i8, i16) as promoted
This means the output of LowerFormalArguments returns a lowered
SDValue with the correct type (expected in SelectionDAGBuilder).
Without this, an assertion under a DEBUG macro triggers when those
types are passed on the stack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210102 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-03 13:54:53 +00:00
Jiangning Liu
9a2d239740 [AArch64] Correctly deal with VPR stack parameter passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210067 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-03 03:25:09 +00:00
Alp Toker
4a0555250d Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209982 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-31 21:26:28 +00:00
Eric Christopher
c55e193cdd Have the TLOF creation take a Triple rather than needing a subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209937 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-31 00:07:32 +00:00
Tim Northover
d0dbe02fd2 ARM & AArch64: make use of common cmpxchg idioms after expansion
The C and C++ semantics for compare_exchange require it to return a bool
indicating success. This gets mapped to LLVM IR which follows each cmpxchg with
an icmp of the value loaded against the desired value.

When lowered to ldxr/stxr loops, this extra comparison is redundant: its
results are implicit in the control-flow of the function.

This commit makes two changes: it replaces that icmp with appropriate PHI
nodes, and then makes sure earlyCSE is called after expansion to actually make
use of the opportunities revealed.

I've also added -{arm,aarch64}-enable-atomic-tidy options, so that
existing fragile tests aren't perturbed too much by the change. Many
of them either rely on undef/unreachable too pervasively to be
restored to something well-defined (particularly while making sure
they test the same obscure assert from many years ago), or depend on a
particular CFG shape, which is disrupted by SimplifyCFG.

rdar://problem/16227836

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-30 10:09:59 +00:00
Artyom Skrobov
897fd5f0ed Restore getInvertedCondCode() from the phased-out backend, fixing disassembly for NV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209803 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 11:34:50 +00:00
Artyom Skrobov
684122e84e Add missing check when MatchInstructionImpl() reports failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209802 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 11:26:15 +00:00
Hao Liu
bb7f18abf8 Fix an assertion failure caused by v1i64 in DAGCombiner Shrink.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209798 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 09:19:07 +00:00
Rafael Espindola
665d42accf [pr19844] Add thread local mode to aliases.
This matches gcc's behavior. It also seems natural given that aliases
contain other properties that govern how it is accessed (linkage,
visibility, dll storage).

Clang still has to be updated to expose this feature to C.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209759 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-28 18:15:43 +00:00
Tim Northover
c74a70df6d AArch64: implement copies to/from NZCV as a last ditch effort.
A test in test/Generic creates a DAG where the NZCV output of an ADCS is used
by multiple nodes. This makes LLVM want to save a copy of NZCV for later, which
it couldn't do before.

This should be the last fix required for the aarch64 buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209651 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 12:16:02 +00:00
Tim Northover
9bbb4066f8 AArch64: support 'c' and 'n' inline asm modifiers.
These are tested by test/CodeGen/Generic, so we should probably know
how to deal with them. Fortunately generic code does it if asked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209646 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 07:37:21 +00:00
Tim Northover
e0c2787cb7 AArch64: force i1 to be zero-extended at an ABI boundary.
This commit is debatable. There are two possible approaches, neither
of which is really satisfactory:

1. Use "@foo(i1 zeroext)" to mean an extension to 32-bits on Darwin,
   and 8 bits otherwise.
2. Redefine "@foo(i1)" to mean that the i1 is extended by the caller
   to 8 bits. This goes against the spirit of "zeroext" I think, but
   it's a bit of a vague construct anyway (by definition you're going
   to extend to the amount required by the ABI, that's why it's the
   ABI!).

This implements option 2. The DAG machinery really isn't setup for the
first (there's a fairly strong assumption that "zeroext" goes to at
least the smallest register size), and even if it was the resulting
DAG looks like it would be inferior in many cases.

Theoretically we could add AssertZext nodes in the consumers of
ABI-passed values too now, but this actually seems to make the code
worse in practice by making truncation proceed in two steps. The code
produced is equally valid if we continue to assume only the low bit is
defined.

Should fix PR19850

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209637 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 17:22:07 +00:00
Tim Northover
4146695fb2 AArch64: simplify calling conventions slightly.
We can eliminate the custom C++ code in favour of some TableGen to
check the same things. Functionality should be identical, except for a
buffer overrun that was present in the C++ code and meant webkit
failed if any small argument needed to be passed on the stack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-26 17:21:53 +00:00
Tim Northover
0fc41252ba AArch64: disable FastISel for large code model.
The code emitted is what would be expected for the small model, so it
shouldn't be used when objects can be the full 64-bits away.

This fixes MCJIT tests on Linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209585 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 19:45:41 +00:00