6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-16 11:30:51 +00:00
Code Issues Projects Releases Wiki Activity
38,732 Commits 39 Branches 0 Tags 277 MiB
77f0b7a50a
Commit Graph

8975 Commits

Author SHA1 Message Date
Evan Cheng
77f0b7a50a Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset. 
pshufd $1, (%rdi), %xmm0
        movd %xmm0, %eax
=>
        movl 4(%rdi), %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51026 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-13 08:35:03 +00:00
Nate Begeman
c9bdb00683 Fix and encoding error in the psrad xmm, imm8 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51020 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-13 01:47:52 +00:00
Evan Cheng
fa7fd33a26 On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51019 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-13 00:54:02 +00:00
Dan Gohman
844731a7f1 Clean up the use of static and anonymous namespaces. This turned up 
several things that were neither in an anonymous namespace nor static
but not intended to be global.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-13 00:00:25 +00:00
Nate Begeman
0d1704b955 Teach Legalize how to scalarize VSETCC 
Teach X86 a few more vsetcc patterns.  Custom lowering for unsupported ones is next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51009 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-12 23:09:43 +00:00
Evan Cheng
9bfa03c6fd Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51008 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-12 23:04:07 +00:00
Bill Wendling
9f8fea3531 Constify the machine instruction passed into the 
"is{Trivially,Really}ReMaterializable" methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-12 20:54:26 +00:00
Nate Begeman
c2616e43fd Initial X86 codegen support for VSETCC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-12 20:34:32 +00:00
Dan Gohman
9499b7186b Fix a copy+paste bug; pseudo-instructions shouldn't have 
encoding information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50997 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-12 20:22:45 +00:00
Evan Cheng
ad4196b44a Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50991 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-12 19:56:52 +00:00
Nate Begeman
b43e9c1965 Add support for vicmp/vfcmp codegen, more legalize support coming. 
This is necessary to unbreak the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50988 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-12 19:40:03 +00:00
Dan Gohman
2ce3898e41 Fix a compile error on compilers that still want a return value 
in a non-void function that calls abort.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50969 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-12 16:17:19 +00:00
Anton Korobeynikov
64d69102a1 Add note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50959 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-11 14:33:15 +00:00
Evan Cheng
50d9e7289b When transforming a vector_shuffle to a load, the base address must not be an undef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50940 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-10 06:46:49 +00:00
Dan Gohman
9018e836fe For now, abort when an ISD::VAARG is encountered on x86-64, rather 
than silently generate invalid code.

llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50930 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-10 01:26:14 +00:00
Evan Cheng
b70ea0bd03 Some clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50929 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-10 00:59:18 +00:00
Evan Cheng
25210da757 If movl top bits are undef, let it be selected to movlps, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50928 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-10 00:58:41 +00:00
Evan Cheng
23573e5be6 Add a pattern to do move the low element of a v4f32 and zero extend the rest. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50922 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-09 23:37:55 +00:00
Evan Cheng
d880b97257 Handle a few more cases of folding load i64 into xmm and zero top bits. 
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-09 21:53:03 +00:00
Evan Cheng
fd17f42bab Use movq to move low half of XMM register and zero-extend the rest. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50874 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-08 22:35:02 +00:00
Evan Cheng
7e2ff77ef0 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-08 00:57:18 +00:00
Duncan Sands
671fa97a4b Output correct exception handling and frame info 
on x86-64 linux.  This causes no regressions on
32 bit linux and 32 bit ppc.  More tests pass
on 64 bit ppc with no regressions.  I didn't
turn on eh on 64 bit linux because the intrinsics
needed to compile the eh runtime aren't done
yet.  But if you turn it on and link with the
mainline runtime then eh seems to work fine
on x86-64 linux with this patch.  Thanks to
Dale for testing.  The main point of the patch
is that if you output that some object is
encoded using 4 bytes you had better not output
8 bytes for it: the patch makes everything
consistent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50825 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-07 19:11:09 +00:00
Chris Lattner
3bf6accfea Match things like 'armv5tejl-unknown-linux-gnu' for PR2290 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50698 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-06 02:29:28 +00:00
Dan Gohman
4a3f6c8882 Make several variable declarations static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50696 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-06 01:53:16 +00:00
Chris Lattner
88c1baa50c add a micro optzn. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50681 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 23:19:45 +00:00
Mon P Wang
ab3e747c64 Improved generated code for atomic operators 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50677 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 22:56:23 +00:00
Evan Cheng
71f489d728 Code clean up. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50675 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 22:12:23 +00:00
Mon P Wang
63307c335a Added addition atomic instrinsics and, or, xor, min, and max. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 19:05:59 +00:00
Dan Gohman
94bbdc8c25 Fix IsLinux being uninitialized on non-Linux targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50660 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 18:43:07 +00:00
Anton Korobeynikov
aa57a7f7a1 Fix 80col violation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50654 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 17:08:59 +00:00
Dan Gohman
600bf16cf7 Use a dedicated IsLinux flag instead of an ELFLinux TargetType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50649 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 16:11:31 +00:00
Dan Gohman
a779a9899a Add AsmPrinter support for emitting a directive to declare that 
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 00:28:39 +00:00
Anton Korobeynikov
6625eff8ec Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern), 
but should work. Work is in progress, more models will follow


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50630 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-04 21:36:32 +00:00
Evan Cheng
5759f97f50 Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-04 09:15:50 +00:00
Evan Cheng
22b942aa4d Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-03 00:52:09 +00:00
Evan Cheng
082f1161b1 Undo r50574. We are already ensuring the folded load address is 16-byte aligned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50578 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-02 17:01:01 +00:00
Evan Cheng
b609339a5c 80 column violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50575 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-02 07:53:32 +00:00
Evan Cheng
ef6a512489 Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50574 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-02 07:50:58 +00:00
Arnold Schwaighofer
30e62c098b Tail call optimization improvements: 
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.

Initial PowerPC tail call implementation:

Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).  
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if 
  caller and callee are fastcc
  call is a tail call (in tail call position, call followed by ret)
  no variable argument lists or byval arguments
  option -tailcallopt is enabled
Supported:
 * non pic tail calls on linux/darwin
 * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
 * inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.

A test checking the argument lowering behaviour on x86-64 was added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-30 09:16:33 +00:00
Scott Michel
203b2d6eed Bug fixes and updates for CellSPU, syncing up with trunk. Most notable 
fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50462 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-30 00:30:08 +00:00
Anton Korobeynikov
966e7997b5 Don't do stupid things: doInitialization(Module&) is not applicable to ModulePass :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50433 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-29 18:16:22 +00:00
Dan Gohman
1f13c686df Fix the SVOffset values for loads and stores produced by 
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50359 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-28 17:15:20 +00:00
Anton Korobeynikov
2810d675f8 Fix FP return for Win64 ABI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50342 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-28 07:40:07 +00:00
Anton Korobeynikov
998a5bcc80 Properly lower vararg's FORMAL_ARGUMENTS node on win64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50325 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-27 23:15:03 +00:00
Anton Korobeynikov
7255193b4f Handle fp80 for win64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50324 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-27 22:54:09 +00:00
Chris Lattner
5e764233f3 A few inline asm cleanups: 
- Make targetlowering.h fit in 80 cols.
  - Make LowerAsmOperandForConstraint const.
  - Make lowerXConstraint -> LowerXConstraint
  - Make LowerXConstraint return a const char* instead of taking a string byref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50312 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-26 23:02:14 +00:00
Chris Lattner
2ba1c06d48 no need to implement this method and just have it call 
the default impl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50311 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-26 22:59:59 +00:00
Evan Cheng
44c0fd17e1 Extract the lower 64-bit if a MMX value is passed in a XMM register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50292 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-25 20:13:28 +00:00
Evan Cheng
082948df9b Fix illegal MMX_MOVDQ2Qrr pattern. vector_extract result must be a scalar value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50291 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-25 20:12:46 +00:00
Evan Cheng
10e864276b Special handling for MMX values being passed in either GPR64 or lower 64-bits of XMM registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50289 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-25 19:11:04 +00:00